| 1. |
- Kyriakakis, Eleftherios, et al.
(författare)
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Implementation of a Fault-Tolerant, Globally-Asynchronous-Locally-Synchronous, Inter-Chip NoC Communication Bridge on FPGAs
- 2017
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Ingår i: Proceeding of the 2017 IEEE nordic circuits and systems conference (norcas). - : IEEE. ; , s. -6
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Konferensbidrag (refereegranskat)abstract
- Network-on-Chip (NoC) architectures were introduced to help mitigate the bottleneck and scalability issues faced by the traditional bus interconnect in Multi-Processor System-On Chip (MPSoC). Nowadays, many embedded systems host a significant number of micro-controllers and processors (i.e. vehicles, airplanes, satellites, etc.) and as this number continues to increase, traditional bus solutions will start to fail on those platforms as well. NoCs not only offer a scalable solution for MPSoC interconnects but they can also provide a uniform platform of communication to embedded systems with multiple off-chip, often heterogeneous, processors. This leads to the need for investigation on inter-chip communication bridges suitable for transmitting flits/packets across chips and possibly across clock domains. This paper investigates an inter-chip communication link, of an MPSoC NoC architecture which is extended with an off-chip, heterogeneous processor (node) and proposes a scalable, fault-tolerant, globally asynchronous locally synchronous bridge for inter-chip communication. The proposed bridge is implemented on a prototype board of the SEUD KTH experiment where it successfully enables the communication of a NoC distributed over two FPGAs. The inter-chip bridge is verified in-circuit achieving transfer speeds up to 24 MByte/s (approximate to 1.5 Mflit/s) and its ability to correct single bit errors is demonstrated in simulation.
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| 2. |
- Kyriakakis, Eleftherios, et al.
(författare)
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Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller
- 2017
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Ingår i: Proceedings of the 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS). - : IEEE.
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Konferensbidrag (refereegranskat)abstract
- From deep space missions to low-earth orbit satellites, the natural radiation of space proves to be a hostile environment for electronics. Memory elements in particular are highly susceptible to radiation charge that if latched can cause single-event upsets (SEU, bit-flips) which lead to data corruption and even mission critical failures. On Earth, SDRAM devices are widely used as a cost-effective, high performance storage elements in almost every computer system. However, their physical design makes them highly susceptible to SEUs. Thus, their usage in space application is limited and usually avoided, requiring the use of radiation hardened components which are generally a few generations older and often much more expensive than COTS. In this paper, an off-chip SEU/MBU mitigation mechanism is presented that aims to drastically reduce the probability of data corruption inside a commercial-off-the-shelf (COTS) synchronous dynamic random access memory (SDRAM) using a triple modular redundant (TMR) scheme for data and periodic scrubbing. The proposed mitigation technique is implemented in a novel controller that will be used by the single-event upset detector (SEUD) experiment aboard the KTH MInature STudent (MIST) satellite project.
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| 3. |
- Ngo, Kalle
(författare)
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Side-Channel Analysis of Post-Quantum Cryptographic Algorithms
- 2023
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Public key cryptographic schemes used today rely on the intractability of certain mathematical problems that are known to be efficiently solvable with a large-scale quantum computer. To address the need for long-term security, in 2016 NIST started a project for standardizing post-quantum cryptography (PQC) primitives that rely on problems not known to be targets for a quantum computer, such as lattice problems. However, algorithms that are secure from the point of view of traditional cryptanalysis can be susceptible to side-channel attacks. Therefore, NIST put a major emphasis on evaluating the resistance of candidate algorithms to side-channel attacks.This thesis focuses on investigating the susceptibility of two NIST PQC candidates, Saber and CRYSTALS-Kyber Key Encapsulation Mechanisms (KEMs), to side-channel attacks. We present a collection of nine papers, of which eight focus on side-channel analysis of Saber and CRYSTALS-Kyber, and one demonstrates a passive side-channel attack on a hardware random number generator (RNG) integrated in STM32 MCUs.In the first three papers, we demonstrate attacks on higher-order masked software implementations of Saber and CRYSTALS-Kyber. One of the main contributions is a single-step deep learning message recovery method capable of recovering secrets from a masked implementation directly, without explicitly extracting the random masks. Another main contribution is a new neural network training method called recursive learning, which enables the training of neural networks capable of recovering a message bit with a probability higher than 99% from higher-order masked implementations.In the next two papers, we show that even software implementations of Saber and CRYSTALS-Kyber protected by both first-order masking and shuffling can be compromised. We present two methods for message recovery: Hamming weight-based and Fisher-Yates (FY) index-based. Both approaches are successful in recovering secret keys, with the latter using considerably fewer traces. In addition, we extend the ECC-based secret key recovery method presented in the prior chapter to ECCs with larger code distances.In the last two papers, we consider a different type of side channel amplitude-modulated electromagnetic (EM) emanations. We show that information leaked from implementations of Saber and CRYSTALS-Kyber through amplitude-modulated EM side channels can be used to recover the session and secret keys. The main contribution is a multi-bit error-injection method that allows us to exploit byte-level leakage. We demonstrate the success of our method on an nRF52832 system-on-chip supporting Bluetooth 5 and a hardware implementation of CRYSTALS-Kyber in a Xilinx Artix-7 FPGA.Finally, we present a passive side-channel attack on a hardware TRNG in a commercial integrated circuit in our last paper. We demonstrate that it is possible to train a neural network capable of recovering the Hamming weight of random numbers generated by the RNG from power traces with a higher than 60% probability. We also present a new method for mitigating device inter-variability based on iterative re-training.Overall, our research highlights the importance of evaluating the resistance of candidate PQC algorithm implementations to side-channel attacks and demonstrates the susceptibility of current implementations to various types of side channel analysis. Our findings are expected to provide valuable insights into the design of future PQC algorithms that are resistant to side-channel analysis.
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| 4. |
- Ngo, Kalle, et al.
(författare)
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Towards a Single Event Upset Detector Based on COTS FPGA
- 2017
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Ingår i: Proceedings of the 2017 IEEE Nordic circuits and systems conference (norcas). - : IEEE.
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Konferensbidrag (refereegranskat)abstract
- The Single Event Upset Detector (SEUD) is 3U CubeSat payload experiment that aims to achieve radiation tolerant computing through detection and correction of SEU bit flips on COTS SRAM FPGAs. Our proposed self-healing architecture applies selective TMR, internal configuration memory scrubbing, and partial reconfiguration and intends to demonstrate a cost-effective alternative to Space-grade radiation hardened SRAM FPGAs. This paper presents an overview of the ongoing development of the SEUD architecture and when complete, the SEUD will be tested on board the KTH MIST student CubeSat that is targeting to be launched in late 2020.
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