| 1. |
- Aartsen, M. G., et al.
(författare)
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Very high-energy gamma-ray follow-up program using neutrino triggers from IceCube
- 2016
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Ingår i: Journal of Instrumentation. - 1748-0221. ; 11
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Tidskriftsartikel (refereegranskat)abstract
- We describe and report the status of a neutrino-triggered program in IceCube that generates real-time alerts for gamma-ray follow-up observations by atmospheric-Cherenkov telescopes (MAGIC and VERITAS). While IceCube is capable of monitoring the whole sky continuously, high-energy gamma-ray telescopes have restricted fields of view and in general are unlikely to be observing a potential neutrino-flaring source at the time such neutrinos are recorded. The use of neutrino-triggered alerts thus aims at increasing the availability of simultaneous multi-messenger data during potential neutrino flaring activity, which can increase the discovery potential and constrain the phenomenological interpretation of the high-energy emission of selected source classes (e. g. blazars). The requirements of a fast and stable online analysis of potential neutrino signals and its operation are presented, along with first results of the program operating between 14 March 2012 and 31 December 2015.
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| 2. |
- Papadimitriou, Kyprianos D., et al.
(författare)
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Novel design methods and a tool flow for unleashing dynamic reconfiguration
- 2012
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Ingår i: 15th IEEE International Conference on Computational Science and Engineering, CSE 2012 and 10th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, EUC 2012, Paphos, 5 through 7 December 2012. - 9780769549149 ; , s. 391-398
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Konferensbidrag (refereegranskat)abstract
- During the last few years, there is an increasing interest in mixing software and hardware to serve efficiently different applications. This is due to the heterogeneity characterizing the tasks of an application which require the presence of resources from both worlds, software and hardware. Controlling effectively these resources through an integrated tool flow is a challenging problem and towards this direction only a few efforts exist. In fact, a framework that seamlessly exploits both resources of a platform for executing efficiently an application has not yet come into existence. Moreover, reconfigurable computing often incorporated in such platforms due to its high flexibility and customization, has not yet taken off due to the lack of exploiting its full capabilities. Thus, the capability of reconfigurable devices such as Field Programmable Gate Arrays (FPGAs) to be dynamically reconfigured, i.e. reprogramming part of the chip while other parts of the same chip remain functional, has not yet taken off even in small-scale basis. The inherent difficulty in using the tools to control this technology has kept it back from being adopted by academia and industry alike. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a design methodology and a tool flow that will enable designers to implement effectively and easily a system specification on a platform combining software and reconfigurable resources. The FASTER framework accepts as input a high-level description of the application and the architectural details of the target platform, and through certain steps it can enable the full use of the capabilities of the platform, while at the same time it should be flexible enough so as to balance efficiently performance, power and area. One of the main novelties is the incorporation of partial reconfiguration as an explicit design concept at an early stage of the design flow. We target different applications from the embedded, desktop and high-performance computing domains. In all cases we will demonstrate the effectiveness of the proposed framework in exploiting the inherent parallelism of applications and enabling the runtime adaptation of the platforms to the changing needs of the applications.
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| 3. |
- Santambrogio, M. D., et al.
(författare)
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Smart technologies for effective reconfiguration: The FASTER approach
- 2012
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Ingår i: ReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings. - 9781467325721
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Konferensbidrag (refereegranskat)abstract
- Current and future computing systems increasingly require that their functionality stays flexible after the system is operational, in order to cope with changing user requirements and improvements in system features, i.e. changing protocols and data-coding standards, evolving demands for support of different user applications, and newly emerging applications in communication, computing and consumer electronics. Therefore, extending the functionality and the lifetime of products requires the addition of new functionality to track and satisfy the customers needs and market and technology trends. Many contemporary products along with the software part incorporate hardware accelerators for reasons of performance and power efficiency. While adaptivity of software is straightforward, adaptation of the hardware to changing requirements constitutes a challenging problem requiring delicate solutions. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform which includes a general purpose processor combined with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design time and at run time, the capabilities of partial dynamic reconfiguration. The goal is that for selected application domains, the FASTER toolchain will be able to reduce the design and verification time of complex reconfigurable systems providing additional novel verification features that are not available in existing tool flows.
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| 4. |
- Salami, B., et al.
(författare)
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LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing
- 2020
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Ingår i: PROCEEDINGS OF THE 2020 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2020). - 1530-1591. - 9783981926347 ; , s. 169-174
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Konferensbidrag (refereegranskat)abstract
- The LEGaTO project leverages task-based programming models to provide a software ecosystem for Made in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines. The aim is to attain one order of magnitude energy savings from the edge to the converged cloud/HPC, balanced with the security and resilience challenges. LEGaTO is an ongoing three-year EU H2020 project started in December 2017.
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| 5. |
- Allahgholi, A., et al.
(författare)
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AGIPD 1.0 : The high-speed high dynamic range readout ASIC for the adaptive gain integrating pixel detector at the European XFEL
- 2014
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Ingår i: 2014 IEEE Nuclear Science Symposium and Medical Imaging Conference, NSS/MIC 2014. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781479960972
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Konferensbidrag (refereegranskat)abstract
- AGIPD is a hybrid pixel X-ray detector developed by a collaboration between Deutsches Elektronen-Synchrotron (DESY), Paul-Scherrer-Institute (PSI), University of Hamburg and the University of Bonn. The detector is designed to comply with the requirements of the European XFEL. The radiation tolerant Application Specific Integrated Circuit (ASIC) is designed with the following highlights: high dynamic range, spanning from single photon sensitivity up to 104 × 12.4 keV photons, achieved by the use of dynamic gain switching, auto-selecting one of 3 gains of the charge sensitive pre-amplifier. To cope with the unique features of the European XFEL source, image data is stored in 352 analogue memory cells per pixel. The selected gain is stored in the same way and depth, encoded as one of 3 voltage levels. These memories are operated in random-access mode at 4.5MHz frame rate. Data is read out on a row-by-row basis via multiplexers to the DAQ system for digitisation during the 99.4ms gap between the bunch trains of the European XFEL. The AGIPD 1.0 ASIC features 64×64 pixels with a pixel area of 200×200 μm2. It is bump-bonded to a 500 μm thick silicon sensor. The principles of the chip architecture were proven in different experiments and the ASIC characterization was performed with a series of development prototypes. The mechanical concept of the detector system was developed in close contact with the XFEL beamline scientists to ensure a seamless integration into the beamline setup and is currently being manufactured. The first single module system was successfully tested at APS1 the high dynamic range allows imaging of the direct synchrotron beam along with single photon sensitivity and burst imaging of 352 subsequent frames synchronized to the source.
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| 6. |
- Allahgholi, A., et al.
(författare)
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AGIPD, a high dynamic range fast detector for the European XFEL
- 2015
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Ingår i: Journal of Instrumentation. - 1748-0221. ; 10:1
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Tidskriftsartikel (refereegranskat)abstract
- AGIPD-(Adaptive Gain Integrating Pixel Detector) is a hybrid pixel X-ray detector developed by a collaboration between Deutsches Elektronen-Synchrotron (DESY), Paul-Scherrer-Institut (PSI), University of Hamburg and the University of Bonn. The detector is designed to comply with the requirements of the European XFEL. The radiation tolerant Application Specific Integrated Circuit (ASIC) is designed with the following highlights: high dynamic range, spanning from single photon sensitivity up to 10(4) 12.5keV photons, achieved by the use of the dynamic gain switching technique using 3 possible gains of the charge sensitive preamplifier. In order to store the image data, the ASIC incorporates 352 analog memory cells per pixel, allowing also to store 3 voltage levels corresponding to the selected gain. It is operated in random-access mode at 4.5MHz frame rate. The data acquisition is done during the 99.4ms between the bunch trains. The AGIPD has a pixel area of 200 x 200 m m(2) and a 500 m m thick silicon sensor is used. The architecture principles were proven in different experiments and the ASIC characterization was done with a series of development prototypes. The mechanical concept was developed in the close contact with the XFEL beamline scientists and is now being manufactured. A first single module system was successfully tested at APS.
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| 7. |
- Allahgholi, A., et al.
(författare)
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AGIPD, the electronics for a high speed X-ray imager at the Eu-XFEL
- 2014
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Ingår i: Proceedings of Science. - : Proceedings of Science (PoS).
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Konferensbidrag (refereegranskat)abstract
- The AGIPD (Adaptive Gain Integrated Pixel Detector) X-ray imaging camera will be operated at the X-ray Free Electron Laser, Eu-XFEL, under construction in Hamburg, Germany. Key parameters are 1 million 200 μm square pixels, single 12.4 keV photon detection and a dynamic range to 10 000/pixel/image. The developed sensors, ASICs, PCB-electronics and FPGA firmware acquire individual images per bunch at 27 000 bunches/s, packed into 10 bunch-trains/s with a bunch separation of 222 ns. Bunch-trains are handled by 352 analogue storage cells within each pixel of the ASIC and written during the 0.6msec train delivery. Therefore AGIPD can store 3520 images/s from the delivered 27 000 bunches/s. Random addressing provides reusability of each cell after an image has been declared as low-quality, so that good images can be selected. Digitization is performed between trains (99.4 msec). In the paper all functional blocks are introduced. The details concentrate on the DAQ-chain PCB-electronics and the slow control. A dense area of 1024 ADC-channels, each with a pickup-noise filtering and sampling of up to 50 MS/s/ADC and a serial output of 700 Mbit/s/ADC. FPGAs operate the ASICs synchronized to the bunch structure and collect the bit streams from 64 ADCs/FPGA. Pre-sorted data is transmitted on 10 GbE links out of the camera head using the time between trains. The control and monitoring of the camera with 600 A current consumption is based on a micro-controller and I2C bus with an addressing architecture allowing many devices and identical modules. The high currents require planned return paths at the system level. First experimental experience with the constructed components will be presented.
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| 8. |
- Allahgholi, A., et al.
(författare)
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Front end ASIC for AGIPD, a high dynamic range fast detector for the European XFEL
- 2016
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Ingår i: Journal of Instrumentation. - 1748-0221. ; 11:1
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Tidskriftsartikel (refereegranskat)abstract
- The Adaptive Gain Integrating Pixel Detector (AGIPD) is a hybrid pixel X-ray detector for the European-XFEL. One of the detector's important parts is the radiation tolerant front end ASIC fulfilling the European-XFEL requirements: high dynamic range-from sensitivity to single 12.5keV-photons up to 104 photons. It is implemented using the dynamic gain switching technique with three possible gains of the charge sensitive preamplifier. Each pixel can store up to 352 images in memory operated in random-access mode at >= 4.5MHz frame rate. An external vetoing may be applied to overwrite unwanted frames.
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| 9. |
- Allahgholi, A., et al.
(författare)
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The adaptive gain integrating pixel detector
- 2016
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Ingår i: Journal of Instrumentation. - 1748-0221. ; 11:2
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Tidskriftsartikel (refereegranskat)abstract
- The adaptive gain integrating pixel detector (AGIPD) is a development of a collaboration between Deustsches Elektronen-Synchrotron (DESY), the Paul-Scherrer-Institute (PSI), the University of Hamburg and the University of Bonn. The detector is designed to cope with the demanding challenges of the European XFEL. Therefore it comes along with an adaptive gain stage allowing a high dynamic range, spanning from single photon sensitivity to 10(4) x 12.4 keV photons and 352 analogue memory cells per pixel. The aim of this report is to briefly explain the concepts of the AGIPD electronics and mechanics and then present recent experiments demonstrating the functionality of its key features.
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| 10. |
- Allahgholi, A., et al.
(författare)
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The AGIPD 1.0 ASIC : Random access high frame rate, high dynamic range X-ray camera readout for the European XFEL
- 2015
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Ingår i: 2015 IEEE Nuclear Science Symposium and Medical Imaging Conference, NSS/MIC 2015. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781467398626
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Konferensbidrag (refereegranskat)abstract
- The European XFEL is an extremely brilliant Free Electron Laser Source with a very demanding pulse structure: trains of 2700 X-Ray pulses are repeated at 10 Hz. The pulses inside the train are spaced by 220 ns and each one contains up to 1012 photons of 12.4 keV, while being ≤ 100 fs in length. AGIPD (Adaptive Gain Integrating Pixel Detector) is a hybrid 1M-pixel detector developed by DESY, PSI, and the Universities of Bonn and Hamburg to cope with these properties. Thus the readout ASIC has to provide not only single photon sensitivity and a dynamic range ≳ 104 photons/pixel in the same image but also a memory for as many images of a pulse train as possible for delayed readout prior to the next train. The AGIPD 1.0 ASIC uses a 130 nm CMOS technology and radiation tolerant techniques to withstand the radiation damage incurred by the high impinging photon flux. Each ASIC contains 64 × 64 pixels of 200μmχ200μm. The circuit of each pixel contains a charge sensitive preamplifier with threefold switchable gain, a discriminator for an adaptive gain selection, and a correlated double sampling (CDS) stage to remove reset and low-frequency noise components. The output of the CDS, as well as the dynamically selected gain is sampled in a capacitor-based analogue memory for 352 samples, which occupies about 80% of a pixels area. For readout each pixel features a charge sensitive buffer. A control circuit with a command based interface provides random access to the memory and controls the row-wise readout of the data via multiplexers to four differential analogue ports. The AGIPD 1.0 full scale ASIC has been received back from the foundry in fall of 2013. Since then it has been extensively characterised also with a sensor as a single chip and in 2 × 8-chip modules for the AGIPD 1 Mpix detector. We present the design of the AGIPD 1.0 ASIC along with supporting results, also from beam tests at PETRA III and APS, and show changes incorporated in the recently taped out AGIPD 1.1 ASIC upgrade.
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