| 1. |
- Svensson, Bertil, 1948-, et al.
(författare)
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A running leap for embedded signal processing to future parallel platforms
- 2014
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Ingår i: WISE 2014 - Proceedings of the 2014 ACM International Workshop on Long-Term Industrial Collaboration on Software Engineering, Co-located with ASE 2014. - New York, NY, USA : Association for Computing Machinery, Inc. - 9781450330459 ; , s. 35-42
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Konferensbidrag (refereegranskat)abstract
- This paper highlights the collaboration between industry and academia in research. It describes more than two decades of intensive development and research of new hardware and software platforms to support innovative, high-performance sensor systems with extremely high demands on embedded signal processing capability. The joint research can be seen as the run before a necessary jump to a new kind of computational platform based on parallelism. The collaboration has had several phases, starting with a focus on hardware, then on efficiency, later on software development, and finally on taking the jump and understanding the expected future. In the first part of the paper, these phases and their respective challenges and results are described. Then, in the second part, we reflect upon the motivation for collaboration between company and university, the roles of the partners, the experiences gained and the long-term effects on both sides.
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| 2. |
- Bengtsson, Jerker, et al.
(författare)
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A configurable framework for stream programming exploration in baseband applications
- 2006
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Ingår i: 2006 IEEE International Parallel & Distributed Processing Symposium. - Piscataway, N.J. : IEEE Press. - 1424400546 ; , s. 8-
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Konferensbidrag (refereegranskat)abstract
- This paper presents a configurable framework to be used for rapid prototyping of stream based languages. The framework is based on a set of design patterns defining the elementary structure of a domain specific language for high-performance signal processing. A stream language prototype for baseband processing has been implemented using the framework. We introduce language constructs to efficiently handle dynamic reconfiguration of distributed processing parameters. It is also demonstrated how new language specific primitive data types and operators can be used to efficiently and machine independently express computations on bitfields and data-parallel vectors. These types and operators yield code that is readable, compact and amenable to a stricter type checking than is common practice. They make it possible for a programmer to explicitly express parallelism to be exploited by a compiler. In short, they provide a programming style that is less error prone and has the potential to lead to more efficient implementations.
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| 3. |
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| 4. |
- Bengtsson, Jerker, et al.
(författare)
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Manycore performance analysis using timed configuration graphs
- 2009
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Ingår i: International Symposium on Systems, Architectures, Modeling, and Simulation, 2009. SAMOS '09. - Piscataway, N.J. : IEEE Press. - 9781424445028 ; , s. 108-117
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Konferensbidrag (refereegranskat)abstract
- The programming complexity of increasingly parallel processors calls for new tools to assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed to form part of a tool which is intended for iteratively tuning the mapping of dataflow graphs onto manycores. One of the models is used for capturing the essentials of manycores that are identified as suitable for signal processing and which we use as target architectures. Another model is the intermediate representation in the form of a timed configuration graph, describing the mapping of a dataflow graph onto a machine model. Moreover, this IR can be used for performance evaluation using abstract interpretation. We demonstrate how the models can be configured and applied in order to map applications on the Raw processor. Furthermore, we report promising results on the accuracy of performance predictions produced by our tool. It is also demonstrated that the tool can be used to rank different mappings with respect to optimisation on throughput and end-to-end latency.
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| 5. |
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| 6. |
- Bengtsson, Lars, 1958-, et al.
(författare)
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A high-performance embedded massively parallel processing system
- 1994
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Ingår i: Proceedings of the First International Conference on Massively Parallel Computing Systems (MPCS) The Challenges of General-Purpose and Special-Purpose Computing. - Piscataway, N.J. : IEEE. - 0818663227 - 9780818663222 ; , s. 201-206
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Konferensbidrag (refereegranskat)abstract
- A need to apply the massively parallel computing paradigm in embedded real-time systems is foreseen. Such applications put new demands on massively parallel systems, different from those of general purpose computing. For example, time determinism is more important than maximal throughput, physical distribution is often required, size, power, and I/O are important, and interactive development tools are needed. The paper describes an architecture for high-performance, embedded, massively parallel processing, featuring a large number of nodes physically distributed over a large area. A typical node has thousands of processing elements (PEs) organized in SIMD mode and is the size of the palm of a hand, Intermodule communication over a scalable optical network is described. A combination of wavelength division multiplexing (WDM) and time division multiplexing (TDM) is used. © 1994 IEEE.
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| 7. |
- Bengtsson, Lars, 1958-, et al.
(författare)
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Brains for Autonomous Robots : Hardware and Surgery Tools
- 1994
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Ingår i: Proceedings of PerAc '94. From Perception to Action. - Los Alamitos : IEEE. - 0818664827 - 9780818664823 ; , s. 436-439
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Konferensbidrag (refereegranskat)abstract
- This paper presents a hardware architecture and a software tool needed for future autonomous robots. Specific attention is given to the execution of artificial neural networks and to the need for a good inspection and visualization tool when developing this kind of systems. Achievable performance using state-of-the-art technology is estimated and module miniaturization issues are discussed. © 1994 IEEE.
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| 8. |
- Bengtsson, Lars, 1958-, et al.
(författare)
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REMAP massively parallel computer platform for neural computations
- 1997
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Ingår i: Proceedings of the Third International Conference on Microelectronics for Neural Networks (MicroNeuro’93). ; , s. 47-62
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Konferensbidrag (refereegranskat)abstract
- The REMAP project addresses questions related to the use of massively parallel, distributed computing in embedded systems. Of specific interest is the execution of artificial neural network algorithms on multiple, cooperating processor arrays. This paper concentrates on the recently finished, and currently used, processor array prototype, REMAP-β, of SIMD (Single Instruction stream, Multiple Data streams) type. The architecture and implementation of the computer is described, both its overall structure and its constituent parts. Following this comes a discussion of its use as an architecture laboratory, which stems from the fact that it is implemented using FPGA (Field Programmable Gate Array) circuits. As an architecture laboratory the prototype can be used to implement and evaluate, e.g., various Processing Element (PE) designs. A couple of examples of PE architectures, including one with floating-point support, are given. The mapping of important neural network algorithms on processor arrays of this kind is shown, and possible tuning of the architecture to meet specific processing demands is discussed. Performance figures are given as well as implications for future VLSI implementations of the array.
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| 9. |
- Johnsson, Dennis, et al.
(författare)
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Two-level Reconfigurable Architecture for High-Performance Signal Processing
- 2004
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Ingår i: ERSA'04, The 2004 International Conference on Engineering of Reconfigurable Systems and Algorithms. - Arthens : CSREA Press. - 9781932415421 ; , s. 177-183
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Konferensbidrag (refereegranskat)abstract
- High speed signal processing is often performed as a pipeline of functions on streams or blocks of data. In order to obtain both flexibility and performance, parallel, reconfigurable array structures are suitable for such processing. The array topology can be used both on the micro and macro-levels, i.e. both when mapping a function on a fine-grained array structure and when mapping a set of functions on different nodes in a coarse-grained array. We outline an architecture on the macro-level as well as explore the use of an existing, commercial, word level reconfigurable architecture on the micro-level. We implement an FFT algorithm in order to determine how much of the available resources are needed for controlling the computations. Having no program memory and instruction sequencing available, a large fraction, 70%, of the used resources is used for controlling the computations, but this is still more efficient than having statically dedicated resources for control. Data can stream through the array at maximum I/O rate, while computing FFTs. The paper also shows how pipelining of the FFT algorithm over a two-level reconfigurable array of arrays can be done in various ways, depending on the application demands.
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| 10. |
- Nilsson, Björn, et al.
(författare)
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A snoozing frequency binary tree protocol
- 2010
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Ingår i: The Third International EURASIP Workshop on RFID Technology, La Manga del Mar Menor, Cartagena, Spain, 6-7 Sept, 2010.
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Konferensbidrag (refereegranskat)abstract
- In this paper we describe and evaluate anenhanced version of an active RFID wake-up and tag IDextraction radio communication protocol. The enhancedprotocol further reduces the transponders’ power consumption(prolonging their battery lifetime). The protocol uses afrequency binary tree method for extracting the identificationnumber of each transponder. This protocol is enhanced byextending it with a framed slotted medium access controlmethod which decreases the number of activations of eachtransponder during tag ID extractions. Using this medium accessmethod, the average number of transponder activations isdecreased with a factor of 2.5 compared to the original protocol.The resulting increase in ID read-out delay is 0.9%, on average.
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