| 1. |
- Bengtsson, Lars, 1958-, et al.
(författare)
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A high-performance embedded massively parallel processing system
- 1994
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Ingår i: Proceedings of the First International Conference on Massively Parallel Computing Systems (MPCS) The Challenges of General-Purpose and Special-Purpose Computing. - Piscataway, N.J. : IEEE. - 0818663227 - 9780818663222 ; , s. 201-206
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Konferensbidrag (refereegranskat)abstract
- A need to apply the massively parallel computing paradigm in embedded real-time systems is foreseen. Such applications put new demands on massively parallel systems, different from those of general purpose computing. For example, time determinism is more important than maximal throughput, physical distribution is often required, size, power, and I/O are important, and interactive development tools are needed. The paper describes an architecture for high-performance, embedded, massively parallel processing, featuring a large number of nodes physically distributed over a large area. A typical node has thousands of processing elements (PEs) organized in SIMD mode and is the size of the palm of a hand, Intermodule communication over a scalable optical network is described. A combination of wavelength division multiplexing (WDM) and time division multiplexing (TDM) is used. © 1994 IEEE.
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| 2. |
- Bengtsson, Lars, 1958-, et al.
(författare)
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A processor array module for distributed, massively parallel, embedded computing
- 1993
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Ingår i: Microprocessing and Microprogramming. - Amsterdam : Elsevier. - 0165-6074. ; 38:1-5, s. 529-537
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Tidskriftsartikel (refereegranskat)abstract
- With the increased degree of miniaturization resulting from the use of modem VLSI technology and the high communication bandwidth available through optical connections, it is now possible to build massively parallel computers based on distributed modules which can be embedded in advanced industrial products. Examples of such future possibilities are ''action-oriented systems'', in which a network of highly parallel modules perform a multitude of tasks related to perception, cognition, and action. The paper discusses questions of architecture on the level of modules and inter-module communication and gives concrete architectural solutions which meet the demands of typical, advanced industrial real-time applications. The interface between the processors arrays and the all-optical communication network is described in some detail. Implementation issues specifically related to the demand for miniaturization are discussed.
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| 3. |
- Bengtsson, Lars, 1958-, et al.
(författare)
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Brains for Autonomous Robots : Hardware and Surgery Tools
- 1994
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Ingår i: Proceedings of PerAc '94. From Perception to Action. - Los Alamitos : IEEE. - 0818664827 - 9780818664823 ; , s. 436-439
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Konferensbidrag (refereegranskat)abstract
- This paper presents a hardware architecture and a software tool needed for future autonomous robots. Specific attention is given to the execution of artificial neural networks and to the need for a good inspection and visualization tool when developing this kind of systems. Achievable performance using state-of-the-art technology is estimated and module miniaturization issues are discussed. © 1994 IEEE.
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| 4. |
- Bengtsson, Lars, 1958-, et al.
(författare)
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REMAP massively parallel computer platform for neural computations
- 1997
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Ingår i: Proceedings of the Third International Conference on Microelectronics for Neural Networks (MicroNeuro’93). ; , s. 47-62
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Konferensbidrag (refereegranskat)abstract
- The REMAP project addresses questions related to the use of massively parallel, distributed computing in embedded systems. Of specific interest is the execution of artificial neural network algorithms on multiple, cooperating processor arrays. This paper concentrates on the recently finished, and currently used, processor array prototype, REMAP-β, of SIMD (Single Instruction stream, Multiple Data streams) type. The architecture and implementation of the computer is described, both its overall structure and its constituent parts. Following this comes a discussion of its use as an architecture laboratory, which stems from the fact that it is implemented using FPGA (Field Programmable Gate Array) circuits. As an architecture laboratory the prototype can be used to implement and evaluate, e.g., various Processing Element (PE) designs. A couple of examples of PE architectures, including one with floating-point support, are given. The mapping of important neural network algorithms on processor arrays of this kind is shown, and possible tuning of the architecture to meet specific processing demands is discussed. Performance figures are given as well as implications for future VLSI implementations of the array.
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| 5. |
- Bengtsson, Lars, et al.
(författare)
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The REMAP Reconfigurable Architecture : a Retrospective
- 2006
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Ingår i: FPGA Implementations of Neural Networks. - New York : Springer-Verlag New York. - 0387284850 ; , s. 325-360
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Bokkapitel (refereegranskat)abstract
- The goal of the REMAP project was to gain new knowledge about the design and use of massively parallel computer architectures in embedded real-time systems. In order to support adaptive and learning behavior in such systems, the efficient execution of Artificial Neural Network (ANN) algorithms on regular processor arrays was in focus. The REMAP-β parallel computer built in the project was designed with ANN computations as the main target application area. This chapter gives an overview of the computational requirements found in ANN algorithms in general and motivates the use of regular processor arrays for the efficient execution of such algorithms. REMAP-β was implemented using the FPGA circuits that were available around 1990. The architecture, following the SIMD principle (Single Instruction stream, Multiple Data streams), is described, as well as the mapping of some important and representative ANN algorithms. Implemented in FPGA, the system served as an architecture laboratory. Variations of the architecture are discussed, as well as scalability of fully synchronous SIMD architectures. The design principles of a VLSI-implemented successor of REMAP-β are described, and the paper is concluded with a discussion of how the more powerful FPGA circuits of today could be used in a similar architecture. © 2006 Springer.
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| 6. |
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| 7. |
- Hellquist, Björn, et al.
(författare)
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Structures of Solvated Cations of Palladium(II) and Platinum(II) in Dimethyl Sulfoxide, Acetonitrile and Aqueous Solution Studied by EXAFS and LAXS
- 1991
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Ingår i: Acta Chemica Scandinavica. - : Danish Chemical Society. - 0904-213X. ; 45:5, s. 449-455
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Tidskriftsartikel (refereegranskat)abstract
- X-Ray absorption edge and EXAFS spectra of the solvated cations of platinum(II) in water, dimethyl sulfoxide and acetonitrile and of palladium(II) in dimethyl sulfoxide have been recorded and analyzed. The cations are four-coordinated. Pt-O in Pt(H2O)4(2+) is 2.01(1) angstrom and Pt-N in Pt(CH3CN)4(2+) is 2.00(1) angstrom. The dimethyl sulfoxide solvated cations of both platinum and palladium contain two sulfur- and two oxygen-bonded ligands with Pt-O 2.07(2), Pt-S 2.21(2), Pd-O 2.04(2), and Pd-S 2.23(2) angstrom, probably in a square-planar cis-arrangement, as in the solid state. Large-angle X-ray scattering (LAXS) studies of the platinum(II) dimethyl sulfoxide solvated cation in a solution of the triflate salt gave Pt-O 2.07(1) and Pt-S 2.20(1) angstrom and in a solution of the tetrafluoroborate salt Pt-O 2.07(2) and Pt-S 2.21(5) angstrom, in good agreement with the EXAFS results. Neither technique gave any support for axially bound solvent molecules in addition to the four in the assumed square coordination plane.
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| 8. |
- Nilsson, Björn, et al.
(författare)
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A snoozing frequency binary tree protocol
- 2010
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Ingår i: The Third International EURASIP Workshop on RFID Technology, La Manga del Mar Menor, Cartagena, Spain, 6-7 Sept, 2010.
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Konferensbidrag (refereegranskat)abstract
- In this paper we describe and evaluate anenhanced version of an active RFID wake-up and tag IDextraction radio communication protocol. The enhancedprotocol further reduces the transponders’ power consumption(prolonging their battery lifetime). The protocol uses afrequency binary tree method for extracting the identificationnumber of each transponder. This protocol is enhanced byextending it with a framed slotted medium access controlmethod which decreases the number of activations of eachtransponder during tag ID extractions. Using this medium accessmethod, the average number of transponder activations isdecreased with a factor of 2.5 compared to the original protocol.The resulting increase in ID read-out delay is 0.9%, on average.
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| 9. |
- Nilsson, Björn, 1965-, et al.
(författare)
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An active backscatter wake-up and tag identification extraction protocol for low cost and low power active RFID
- 2010
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Ingår i: Proceedings of 2010 IEEE International Conference on RFID-Technology and Applications, RFID-TA 2010. - Piscataway, NJ : IEEE Press. - 9781424466986 - 9781424467006 ; , s. 86-91
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Konferensbidrag (refereegranskat)abstract
- In this paper we present a Radio Frequency Identification (RFID) protocol used to wake up and extract the ID of every tag (or a subset thereof) within reach of a reader in an active backscatter RFID system. We also study the effect on tag energy cost and read-out delay incurred when using the protocol, which is based on a frequency binary tree. Simulations show that, when using the 2.45 GHz ISM band, more than 1500 tags can be read per second.With a population of 1000 tags, the average read-out delay is 319 ms, and the expected lifetime of the RFID tags is estimated to be more than 2.5 years, even in a scenario when they are read out very often.
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| 10. |
- Nilsson, Björn, et al.
(författare)
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An application dependent medium access protocol for active RFID using dynamic tuning of the back-off algorithm
- 2009
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Ingår i: Proceedings of the 2009 IEEE International Conference on RFID (RFID 2009). - Piscataway, N.J. : IEEE Press. - 9781424433377 ; , s. 72-79
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Konferensbidrag (refereegranskat)abstract
- Active Radio Frequency Identification (A-RFID) is a technology where the tags (transponders) carry an on-board energy source for powering the radio, processor circuits, and sensors. Besides offering longer working distance between RFID reader and tag than passive RFID, this also enables the tags to do sensor measurements, calculations and storage even when no RFID-reader is in the vicinity of the tags. In this paper we introduce a medium access data communication protocol which dynamically adjusts its back-off algorithm to best suit the actual active RFID application at hand. Based on a simulation study of the effect on tag energy cost, readout delay, and message throughput incurred by some typical back-off algorithms in a CSMA/CA (Carrier Sense Multiple Access / Collision Avoidance) A-RFID protocol, we conclude that, by dynamic tuning of the initial contention window size and back-off interval coefficient, tag energy consumption and read-out delay can be significantly lowered. We also present specific guidelines on how parameters should be selected under various application constraints (viz. maximum readout delay; and the number of tags passing).
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