| 1. |
- Svensson, Bertil, 1948-, et al.
(författare)
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A running leap for embedded signal processing to future parallel platforms
- 2014
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Ingår i: WISE 2014 - Proceedings of the 2014 ACM International Workshop on Long-Term Industrial Collaboration on Software Engineering, Co-located with ASE 2014. - New York, NY, USA : Association for Computing Machinery, Inc. - 9781450330459 ; , s. 35-42
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Konferensbidrag (refereegranskat)abstract
- This paper highlights the collaboration between industry and academia in research. It describes more than two decades of intensive development and research of new hardware and software platforms to support innovative, high-performance sensor systems with extremely high demands on embedded signal processing capability. The joint research can be seen as the run before a necessary jump to a new kind of computational platform based on parallelism. The collaboration has had several phases, starting with a focus on hardware, then on efficiency, later on software development, and finally on taking the jump and understanding the expected future. In the first part of the paper, these phases and their respective challenges and results are described. Then, in the second part, we reflect upon the motivation for collaboration between company and university, the roles of the partners, the experiences gained and the long-term effects on both sides.
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| 2. |
- Bengtsson, Jerker, et al.
(författare)
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A configurable framework for stream programming exploration in baseband applications
- 2006
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Ingår i: 2006 IEEE International Parallel & Distributed Processing Symposium. - Piscataway, N.J. : IEEE Press. - 1424400546 ; , s. 8-
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Konferensbidrag (refereegranskat)abstract
- This paper presents a configurable framework to be used for rapid prototyping of stream based languages. The framework is based on a set of design patterns defining the elementary structure of a domain specific language for high-performance signal processing. A stream language prototype for baseband processing has been implemented using the framework. We introduce language constructs to efficiently handle dynamic reconfiguration of distributed processing parameters. It is also demonstrated how new language specific primitive data types and operators can be used to efficiently and machine independently express computations on bitfields and data-parallel vectors. These types and operators yield code that is readable, compact and amenable to a stricter type checking than is common practice. They make it possible for a programmer to explicitly express parallelism to be exploited by a compiler. In short, they provide a programming style that is less error prone and has the potential to lead to more efficient implementations.
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| 3. |
- Bengtsson, Jerker, et al.
(författare)
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A Domain-specific Approach for Software Development on Manycore Platforms
- 2008
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Ingår i: SIGARCH Computer Architecture News. - New York : ACM Press. - 0163-5964 .- 1943-5851. ; 36:5, s. 2-10
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Tidskriftsartikel (refereegranskat)abstract
- The programming complexity of increasingly parallel processors calls for new tools that assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed as part of a tool for mapping dataflow graphs onto manycores. One of the models captures the essentials of manycores identified as suitable for signal processing, and which we use as target for our algorithms. As an intermediate representation we introduce timed configuration graphs, which describe the mapping of a model of an application onto a machine model. Moreover, we show how a timed configuration graph by very simple means can be evaluated using an abstract interpretation to obtain performance feedback. This information can be used by our tool and by the programmer in order to discover improved mappings.
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| 4. |
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| 5. |
- Bengtsson, Jerker, et al.
(författare)
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Manycore performance analysis using timed configuration graphs
- 2009
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Ingår i: International Symposium on Systems, Architectures, Modeling, and Simulation, 2009. SAMOS '09. - Piscataway, N.J. : IEEE Press. - 9781424445028 ; , s. 108-117
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Konferensbidrag (refereegranskat)abstract
- The programming complexity of increasingly parallel processors calls for new tools to assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed to form part of a tool which is intended for iteratively tuning the mapping of dataflow graphs onto manycores. One of the models is used for capturing the essentials of manycores that are identified as suitable for signal processing and which we use as target architectures. Another model is the intermediate representation in the form of a timed configuration graph, describing the mapping of a dataflow graph onto a machine model. Moreover, this IR can be used for performance evaluation using abstract interpretation. We demonstrate how the models can be configured and applied in order to map applications on the Raw processor. Furthermore, we report promising results on the accuracy of performance predictions produced by our tool. It is also demonstrated that the tool can be used to rank different mappings with respect to optimisation on throughput and end-to-end latency.
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| 6. |
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| 7. |
- Bengtsson, Jerker
(författare)
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Models and Methods for Development of DSP Applications on Manycore Processors
- 2009
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Advanced digital signal processing systems require specialized high-performance embedded computer architectures. The term high-performance translates to large amounts of data and computations per time unit. The term embedded further implies requirements on physical size and power efficiency. Thus the requirements are of both functional and non-functional nature. This thesis addresses the development of high-performance digital signal processing systems relying on manycore technology. We propose building two-level hierarchical computer architectures for this domain of applications. Further, we outline a tool flow based on methods and analysis techniques for automated, multi-objective mapping of such applications on distributed memory manycore processors. In particular, the focus is put on how to provide a means for tunable strategies for mapping of task graphs on array structured distributed memory manycores, with respect to given application constraints. We argue for code mapping strategies based on predicted execution performance, which can be used in an auto-tuning feedback loop or to guide manual tuning directed by the programmer. Automated parallelization, optimisation and mapping to a manycore processor benefits from the use of a concurrent programming model as the starting point. Such a model allows the programmer to express different types and granularities of parallelism as well as computation characteristics of importance in the addressed class of applications. The programming model should also abstract away machine dependent hardware details. The analytical study of WCDMA baseband processing in radio base stations, presented in this thesis, suggests dataflow models as a good match to the characteristics of the application and as execution model abstracting computations on a manycore. Construction of portable tools further requires a manycore machine model and an intermediate representation. The models are needed in order to decouple algorithms, used to transform and map application software, from hardware. We propose a manycore machine model that captures common hardware resources, as well as resource dependent performance metrics for parallel computation and communication. Further, we have developed a multifunctional intermediate representation, which can be used as source for code generation and for dynamic execution analysis. Finally, we demonstrate how we can dynamically analyse execution using abstract interpretation on the intermediate representation. It is shown that the performance predictions can be used to accurately rank different mappings by best throughput or shortest end-to-end computation latency.
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| 8. |
- Bengtsson, Lars, 1958-, et al.
(författare)
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A high-performance embedded massively parallel processing system
- 1994
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Ingår i: Proceedings of the First International Conference on Massively Parallel Computing Systems (MPCS) The Challenges of General-Purpose and Special-Purpose Computing. - Piscataway, N.J. : IEEE. - 0818663227 - 9780818663222 ; , s. 201-206
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Konferensbidrag (refereegranskat)abstract
- A need to apply the massively parallel computing paradigm in embedded real-time systems is foreseen. Such applications put new demands on massively parallel systems, different from those of general purpose computing. For example, time determinism is more important than maximal throughput, physical distribution is often required, size, power, and I/O are important, and interactive development tools are needed. The paper describes an architecture for high-performance, embedded, massively parallel processing, featuring a large number of nodes physically distributed over a large area. A typical node has thousands of processing elements (PEs) organized in SIMD mode and is the size of the palm of a hand, Intermodule communication over a scalable optical network is described. A combination of wavelength division multiplexing (WDM) and time division multiplexing (TDM) is used. © 1994 IEEE.
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| 9. |
- Bengtsson, Lars, 1958-, et al.
(författare)
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A processor array module for distributed, massively parallel, embedded computing
- 1993
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Ingår i: Microprocessing and Microprogramming. - Amsterdam : Elsevier. - 0165-6074. ; 38:1-5, s. 529-537
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Tidskriftsartikel (refereegranskat)abstract
- With the increased degree of miniaturization resulting from the use of modem VLSI technology and the high communication bandwidth available through optical connections, it is now possible to build massively parallel computers based on distributed modules which can be embedded in advanced industrial products. Examples of such future possibilities are ''action-oriented systems'', in which a network of highly parallel modules perform a multitude of tasks related to perception, cognition, and action. The paper discusses questions of architecture on the level of modules and inter-module communication and gives concrete architectural solutions which meet the demands of typical, advanced industrial real-time applications. The interface between the processors arrays and the all-optical communication network is described in some detail. Implementation issues specifically related to the demand for miniaturization are discussed.
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| 10. |
- Bengtsson, Lars, 1958-, et al.
(författare)
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Brains for Autonomous Robots : Hardware and Surgery Tools
- 1994
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Ingår i: Proceedings of PerAc '94. From Perception to Action. - Los Alamitos : IEEE. - 0818664827 - 9780818664823 ; , s. 436-439
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Konferensbidrag (refereegranskat)abstract
- This paper presents a hardware architecture and a software tool needed for future autonomous robots. Specific attention is given to the execution of artificial neural networks and to the need for a good inspection and visualization tool when developing this kind of systems. Achievable performance using state-of-the-art technology is estimated and module miniaturization issues are discussed. © 1994 IEEE.
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