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Träfflista för sökning "WFRF:(Bertozzi Davide) ;pers:(Bertozzi Davide)"

Sökning: WFRF:(Bertozzi Davide) > Bertozzi Davide

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1.
  • Al-Khatib, Iyad, et al. (författare)
  • A Multiprocessor System-on-Chip for Real-Time Biomedical Monitoring and Analysis : Architectural Design Space Exploration
  • 2006
  • Ingår i: DAC '06. - New York, New York, USA : ACM Press. ; , s. 125-130
  • Konferensbidrag (refereegranskat)abstract
    • In this paper we focus on MPSoC architectures for human heart ECGreal-time monitoring and analysis. This is a very relevant bio-medicalapplication, with a huge potential market, hence it is an ideal targetfor an application-specific SoC implementation. We investigate asymmetric multi-processor architecture based on STMicroelectronicsVLIW DSPs that process in real-time 12-lead ECG signals. Thisarchitecture improves upon state-of-the-art SoC designs for ECGanalysis in its ability to analyze the full 12 leads in real-time, evenwith high sampling frequencies, and ability to detect heartmalfunction. We explore the design space by considering a number ofhardware and software architectural options.
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2.
  • Al Khatib, Iyad, et al. (författare)
  • Hardware/Software architecture for real-time ECG monitoring and analysis leveraging MPSoC technology
  • 2007
  • Ingår i: Transactions on High-Performance Embedded Architectures and Compilers I. - Berlin, Heidelberg : Springer Berlin Heidelberg. - 9783540715276 ; , s. 239-258
  • Konferensbidrag (refereegranskat)abstract
    • The interest in high performance chip architectures for biomedical applications is gaining a lot of research and market interest. Heart diseases remain by far the main cause of death and a challenging problem for biomedical engineers to monitor and analyze. Electrocardiography (ECG) is an essential practice in heart medicine. However, ECG analysis still faces computational challenges, especially when 12 lead signals are to be analyzed in parallel, in real time, and under increasing sampling frequencies. Another challenge is the analysis of huge amounts of data that may grow to days of recordings. Nowadays, doctors use eyeball monitoring of the 12-lead ECG paper readout, which may seriously impair analysis accuracy. Our solution leverages the advance in multi-processor system-on-chip architectures, and it is centered on the parallelization of the ECG computation kernel. Our Hardware- Software (HW/SW) Multi-Processor System-on-Chip (MPSoQ design improves upon state-of-the-art mostly for its capability to perform real-time analysis of input data, leveraging the computation horsepower provided by many concurrent DSPs, more accurate diagnosis of cardiac diseases, and prompter reaction to abnormal heart alterations. The design methodology to go from the 12-lead ECG application specification to the final HW/SW architecture is the focus of this paper. We explore the design space by considering a number of hardware and software architectural variants, and deploy industrial components to build up the system.
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3.
  • Al-Khatib, Iyad, et al. (författare)
  • Performance Analysis and Design Space Exploration for High-End Biomedical Applications : Challenges and Solutions
  • 2007
  • Ingår i: Proceedings of the International Conference on Hardware - Software Codesign and System Synthesis. - New York, NY, USA : ACM. - 9781595938244 ; , s. 217-226
  • Konferensbidrag (refereegranskat)abstract
    • High-end biomedical applications are a good target for specific-purpose system-on-chip (SoC) implementations. Human heart electrocardiogram (ECG) real-time monitoring andanalysis is an immediate example with a large potential market. Today, the lack of scalable hardware platforms limits real-time analysis capabilities of most portable ECG analyzers, and prevents the upgrade of analysis algorithms for better accuracy. Multiprocessor system-on-chip (MPSoC) technology, which is becoming main-stream in the domain of high-performance microprocessors, is becoming attractive even for power-constrained portable applications, due to the capability to provide scalable computation horsepower at an affordable power cost. This paper illustrates one of the first comprehensive HW/SW exploration frameworks to fully exploit MPSoC technology to improve the quality of real-time ECG analysis.
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4.
  • Bertozzi, Davide, et al. (författare)
  • Networks-on-Chip : Emerging Research Topics and Novel Ideas (Editorial)
  • 2007
  • Ingår i: VLSI design (Print). - : Hindawi Limited. - 1065-514X .- 1563-5171. ; 2007, s. ID: 26454-
  • Tidskriftsartikel (populärvet., debatt m.m.)abstract
    • Network-on-chip- (NoC-) based application-specific systems on chip, where information traffic is heterogeneous and delay requirements may largely vary, require individual capacity assignment for each link in the NoC. This is in contrast to the standard approach of on- and off-chip interconnection networks which employ uniform-capacity links. Therefore, the allocation of link capacities is an essential step in the automated design process of NoC-based systems. The algorithm should minimize the communication resource costs under Quality-of-Service timing constraints. This paper presents a novel analytical delay model for virtual channeled wormhole networks with nonuniform links and applies the analysis in devising an efficient capacity allocation algorithm which assigns link capacities such that packet delay requirements for each flow are satisfied.
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5.
  • Jafari, Fahimeh, 1980- (författare)
  • Analysis and Management of Communication in On-Chip Networks
  • 2015
  • Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
    • Regarding the needs of low-power, high-performance embedded systems and the growing computation-intensive applications, the number of computing resources in a single chip has enormously increased. The current VLSI technology is able to support such an integration of transistors and add many computing resources such as CPU, DSP, specific IPs, etc to build a Systemon- Chip (SoC). However, interconnection between resources becomes another challenging issue which can be raised by using an on-chip interconnection network or Network-on-Chip (NoC). NoC-based communication which allows pipelined concurrent transmissions of transactions is becoming a dominate infrastructure for many core computing platforms.This thesis analyzes and manages both Best Effort (BE) and Guaranteed Service (GS) communications using analytical performance approaches. As the first step, the present thesis focuses on the flow control for BE traffic in NoC. It models BE source rates as the solution to a utility-based optimization problem which is constrained with link capacities while preserving GS traffic requirements at the desired level. Towards this, several utility functions including proportionally-fair, rate-sum, and max-min fair scenarios are investigated. Moreover, it is worth looking into a scenario in which BE source rates are determined in favor of minimizing the delay of such traffics. The presented flow control algorithms solve the proposed optimization problems determining injection rate in each BE source node.In the next step, real-time systems with guaranteed service are considered. Real-time applications require performance guarantees even under worst-case conditions, i.e. Quality of Service (QoS). Using network calculus, we present and prove the required theorems for deriving performance metrics and then apply them to propose formal approaches for the worst-case performance analysis. The proposed analytical model is used to minimize total cost in the networks in terms of buffer and delay. To this end, we address several optimization problems and solve them to consider the impact of various objective functions. We also develop a tool which derives performance metrics for a given NoC, formulates and solves the considerable optimization problems to provide an invaluable insight for NoC designers.
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6.
  • Khatib, Iyad Al, et al. (författare)
  • A multiprocessor system-on-chip for real-time biomedical monitoring and analysis : ECG prototype architectural design space exploration
  • 2008
  • Ingår i: ACM Transactions on Design Automation of Electronic Systems. - : Association for Computing Machinery (ACM). - 1084-4309 .- 1557-7309. ; 13:2, s. 31-
  • Tidskriftsartikel (refereegranskat)abstract
    • In this article we focus on multiprocessor system-on-chip (MPSoC) architectures for human heart electrocardiogram (ECG) real time analysis as a hardware/software (HW/SW) platform offering an advance relative to state-of-the-art solutions. This is a relevant biomedical application with good potential market, since heart diseases are responsible for the largest number of yearly deaths. Hence, it is a good target for an application-specific system-on-chip (SoC) and HW/SW codesign. We investigate a symmetric multiprocessor architecture based on STMicroelectronics VLIW DSPs that process in real time 12-lead ECG signals. This architecture improves upon state-of-the-art SoC designs for ECG analysis in its ability to analyze the full 12 leads in real time, even with high sampling frequencies, and its ability to detect heart malfunction for the whole ECG signal interval. We explore the design space by considering a number of hardware and software architectural options. Comparing our design with present-day solutions from an SoC and application point-of-view shows that our platform can be used in real time and without failures.
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7.
  • Khatib, Iyad Al, et al. (författare)
  • MPSoC ECG biochip : A multiprocessor system-on-chip for real-time human heart monitoring and analysis
  • 2006
  • Ingår i: Proceedings of the 3rd Conference on Computing Frontiers 2006, CF '06. - New York, NY, USA : ACM. - 9781595933027 ; , s. 21-28
  • Konferensbidrag (refereegranskat)abstract
    • The interest in high performance chip architectures for biomedical applications is on the rise. Heart diseases remain by far the main cause of death and a challenging problem for biomedical engineers to monitor and analyze. Electrocardiography (ECG) is an essential practice in heart medicine, which faces computational challenges, especially when 12 lead signals are to be analyzed in parallel, in real time, and under increasing sampling frequencies. Another challenge is the analysis of huge amounts of data that may grow to days of recordings. Nowadays, doctors use eyeball monitoring of the 12-lead ECG paper readout, which may seriously impair analysis accuracy. Our solution leverages the advance in multi-processor system-on-chip architectures, and is centered on the parallelization of the ECG computation kernel. It improves upon state-of-the-art mostly for its capability to perform real-time analysis of input data, leveraging the computation horsepower provided by many concurrent DSPs, more accurate diagnosis of cardiac diseases, and prompter reaction to abnormal heart alterations. The design methodology to go from the 12-lead ECG application specification to the final hardware/software architecture, modeling, and simulation is the focus of this paper. Our system model is based on industrial components. The architectural template we employ is scalable and flexible.
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8.
  • Networks-on-Chip
  • 2007
  • Samlingsverk (redaktörskap) (populärvet., debatt m.m.)
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9.
  • Ruggiero, Martino, et al. (författare)
  • A Cooperative, Accurate Solving Framework for Optimal Allocation, Scheduling and Frequency Selection on Energy-Efficient MPSoCs
  • 2006
  • Ingår i: Intl. Symposium on System-on-Chip SOC06,2006.
  • Konferensbidrag (refereegranskat)abstract
    • Most problems addressed by the software optimization flow for multi-processor systems-on-chip (MPSoCs) are NP-complete, and have been traditionally tackled by means of heuristics and highlevel approximations. Complete approaches have been effectively deployed only under unrealistic simplifying assumptions. We propose a novel methodology to formulate and solve to optimality the allocation, scheduling and discrete voltage selection problem for variable voltage/frequency MPSoCs, minimizing the system energy dissipation and the overhead for frequency switching. We integrate the optimization and validation steps to increase the accuracy of cost models and the confidence in quality of results. Two demonstrators are used to show the viability of the proposed methodology.
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10.
  • Ruggiero, Martino, et al. (författare)
  • Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms
  • 2009
  • Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - 0278-0070 .- 1937-4151. ; 28:3, s. 378-391
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper proposes a novel approach to solve the allocation and scheduling problems for variable voltage/frequency multiprocessor systems-on-chip, which minimizes overall system energy dissipation. The optimality of derived system configurations is guaranteed, while the computation efficiency of the optimizer allows for solving problem instances that were traditionally considered beyond reach for exact solvers (optimality gap). Furthermore, this paper illustrates the development- and run-time software infrastructures that assist the user in developing applications and implementing optimizer solutions. The proposed approach guarantees a high level of power, performance, and constraint satisfaction predictability as from validation on the target platform, thus bridging the abstraction gap.
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