| 1. |
- Penolazzi, Sandro, et al.
(författare)
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A General Approach to High-Level Energy and Performance Estimation in SoCs
- 2009
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Ingår i: 22ND INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH 8TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS. - 9780769535067 ; , s. 200-205
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Konferensbidrag (refereegranskat)abstract
- We present a high-level methodology for efficient and accurate estimation of energy and performance in SoCs at Functional Untimed Level. We then validate the proposed method against gate level for accuracy and against TLM-PV for speed. We show that the method is within 15% of gate-level accuracy and in aver-age 28x faster than TLM-PV, for the benchmark applications selected.
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| 2. |
- Penolazzi, Sandro, et al.
(författare)
-
A general approach to high-level energy and performance estimation in system-on-chip architectures
- 2009
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Ingår i: Journal of Low Power Electronics. - : American Scientific Publishers. - 1546-1998. ; 5:3, s. 373-384
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Tidskriftsartikel (refereegranskat)abstract
- We present a high-level methodology for efficient and accurate estimation of energy and performance in SoCs. Differently from the most common approaches, which rely on Transaction-Level Modeling (TLM), we infer energy and performance figures directly from the Functional Untimed Level, by running the algorithmic specification natively on a common host machine. We then validate the proposed method against gate level for accuracy and against TLM-PV for speed. We show that the method is within 17% of gate-level accuracy and in average 28x faster than TLM-PV, for the benchmark applications selected.
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| 3. |
- Penolazzi, Sandro, et al.
(författare)
-
Energy and Performance Model of a SPARC Leon3 Processor
- 2009
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Ingår i: PROCEEDINGS OF THE 2009 12TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, ARCHITECTURES, METHODS AND TOOLS. - LOS ALAMITOS : IEEE COMPUTER SOC. - 9780769537825 ; , s. 651-656
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Konferensbidrag (refereegranskat)abstract
- We present a general methodology to implement a processor energy model, based on instruction-level characterization, and we apply it to a SPARC-based Leon3 processor. The model is characterized by simulating back-annotated gate-level netlist and has two levels of accuracy: a coarse-grain estimation based on characterizing each single instruction and a fine-grain estimation accounting for the impact of instructions interdependency on energy and based on characterizing pairs of instructions together. Our investigation also keeps into account the effect that both data switching activity and registers correlation have on energy. We validate our model by applying it to a set of instruction traces generated by Instruction Set Simulation and compare it to extracting energy directly from gate level. We achieve a worst-case error similar or equal to 12% and a speedup higher than 1000 times.
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