| 1. |
- Malik, Jamshaid, et al.
(författare)
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An efficient hardware implementation of high quality AWGN generator using Box-Muller method
- 2011
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Ingår i: 11th International Symposium on Communications and Information Technologies, ISCIT 2011. - 9781457712944 ; , s. 449-454
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Konferensbidrag (refereegranskat)abstract
- Box Muller (BM) algorithm is extensively used for generation of high quality Gaussian Random Numbers (GRNs) in hardware. Most efficient published implementation of BM method utilizes transformation of 32-bit data path to 16 bits and use of first degree piece-wise polynomial approximation to compute logarithmic and square root functions. In this work, we have performed extensive error analysis to show that coefficient memory for polynomial approximation can be reduced by more than 35 percent without compromising on quality of generated Gaussian samples. This also reduces complexity of corresponding address generator, which requires most hardware resources. We have also used more efficient and statistically accurate skip-ahead Linear Feedback Shift Registers to generate uniformly distributed numbers for the BM algorithm. Complete hardware implementation utilizes only 407 slices, 03 DSP blocks and 1.5 memory blocks on Xilinx Virtex-4 XC4VLX15 operating at 230 MHz while providing a tail accuracy of 6.6σ. This is better in terms of accuracy and hardware utilization than any of the previously reported architecture.
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| 2. |
- Malik, Jamshaid, et al.
(författare)
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Generating high tail accuracy Gaussian Random Numbers in hardware using central limit theorem
- 2011
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Ingår i: 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011. - 9781457701719 ; , s. 60-65
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Konferensbidrag (refereegranskat)abstract
- An efficient hardware implementation of Gaussian Random Number (GRN) generator based on Central Limit Theorem (CLT) is presented. CLT, although very simple to implement, is never used to generate high quality Gaussian numbers. This is due to the fact that direct implementation of CLT provides very poor accuracy in tail regions of the probability density function. In this work, we have shown that it is possible to achieve high tail accuracy by empirically computing the error in CLT, which can be compensated with a simple correction algorithm. The error has been modeled as first degree piece-wise polynomial approximation, using a novel non-uniform segmentation algorithm to compute the coefficients of polynomial segments. A novel hardware architecture of GRN generator is presented which requires only 420 slices and 1 DSP block of Xilinx Virtex-4 XC4VLX15 operating at 220 MHz. This resource utilization is better than any of the previously reported designs. Demonstrated for the tail accuracy of 6σ, the GRN generator design is scalable to achieve even higher accuracy with minimal increase in hardware resources. The accuracy of GRN generator is validated using statistical goodness of fit tests.
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| 3. |
- Malik, Jamshaid, et al.
(författare)
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Impact of Interpolation Techniques on Statistical Properties and Speed of Fading Channel Simulators
- 2010
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Ingår i: 6th International Conference on Wireless and Mobile Communications, ICWMC 2010. - 9780769541822 ; , s. 117-124
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Konferensbidrag (refereegranskat)abstract
- Interpolation filters are considered to be computationally intensive sections of fading channel simulators. They can be implemented by using linear interpolation or zero-padding followed by low-pass IIR or polyphase filtering. In this work, we will investigate how different interpolation techniques affect statistical properties and speed of the simulator.We will show that use of linear interpolation results in 3 to 6 times improvement in simulation speed while there is negligible degradation in desired statistical accuracy. We will validate this claim by designing a fading channel simulator that uses the above mentioned three interpolation techniques and observing their impact on its first order (probability density functions) and second order (correlation functions) statistical properties.We will also compare the impact of interpolation techniques on the level crossing rate (LCR) and bit error rate (BER) of the fading signal. Finally, we will emphasize our claim by using an advance multiple-tap channel model (gsmTUX6C1) with our simulator (using linear interpolation) and showing that its performance is comparable to corresponding Matlab model that uses polyphase interpolation. We will conclude this work with a recommendation to use linear interpolation for efficient and statistically correct fading channel simulators.
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| 4. |
- Malik, J. S., et al.
(författare)
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Improving performance of fading channel simulators by use of Uniformly distributed Random Numbers
- 2011
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Ingår i: 2010 IEEE International Symposium on Signal Processing and Information Technology. - 9781424499908 ; , s. 91-96
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Konferensbidrag (refereegranskat)abstract
- Filter-based fading channel simulators universally use White Gaussian Noise (WGN) to generate complex tap coefficients. In this work, we will show that replacing WGN source by Uniform Random Number Generator (URNG) results in improved simulation speed in case of software simulator; and reduced area/power in case of hardware simulator. We will verify, both analytically and through extensive simulations, that use of URNG does not cause any degradation in important simulator performance parameters like statistical properties, spectral shape, level crossing rate and bit error rate. To validate our analysis, we have designed fading channel simulators both in software and hardware. We will show that use of URNG causes 6 percent improvement in simulation time in case of software simulator. Similarly, we will demonstrate that for a hardware simulator, we obtain an improvement of 30 and 40 percent in area and power consumption respectively.
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| 5. |
- Malik, Jamshaid Sarwar, et al.
(författare)
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Revisiting central limit theorem : Accurate Gaussian random number generation in VLSI
- 2015
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Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - 1063-8210 .- 1557-9999. ; 23:5, s. 842-855
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Tidskriftsartikel (refereegranskat)abstract
- Gaussian random numbers (GRNs) generated by central limit theorem (CLT) suffer from errors due to deviation from ideal Gaussian behavior for any finite number of additions. In this paper, we will show that it is possible to compensate the error in CLT, thereby correcting the resultant probability density function, particularly in the tail regions. We will provide a detailed mathematical analysis to quantify the error in CLT. This provides a design space with more than four degrees of freedom to build a variety of GRN generators (GRNGs). A framework utilizes this design space to generate customized hardware architectures. We will demonstrate designs of five different architectures of GRNGs, which vary in terms of consumed memory, logic slices, and multipliers on field-programmable gate array. Similarly, depending upon application, these architectures exhibit statistical accuracy from low (4 σ ) to extremely high (12 σ). A comparison with previously published designs clearly indicate advantages of this methodology in terms of both consumed hardware resources and accuracy. We will also provide synthesis results of same designs in application-specific integrated circuit using 65-nm standard cell library. Finally, we will highlight some shortcomings associated with such architectures followed by their remedies.
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| 6. |
- Malik, Jamshaid Sarwar, et al.
(författare)
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Unifying CORDIC and Box-Muller algorithms : An accurate and efficient Gaussian Random Number generator
- 2013
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Ingår i: Proceedings Of The 2013 IEEE 24th International Conference On Application-Specific Systems, Architectures And Processors (ASAP 13). - : IEEE Computer Society. - 9781479904921 ; , s. 277-280
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Konferensbidrag (refereegranskat)abstract
- An efficient hardware implementation of Gaussian Random Number (GRN) generator based upon Box-Muller (BM) and CORDIC algorithms is presented. We will illustrate a novel hardware architecture with flexible design space that unifies the two algorithms. A major advantage of this work is that unlike any of the previously reported architectures, it is possible to eliminate hardware multipliers and memory blocks in the synthesized hardware. This is achieved without compromising on statistical accuracy of GRN generators which is proved both through error analysis and standard tests. We will also demonstrate two different hardware implementations that vary in terms of speed, tail accuracy (4.7σ to 9.4σ), and utilization of hardware resources such as DSP blocks, logic slices and memory blocks on FPGAs. Finally, we will present a comparison of designed architectures with previously published hardware GRN generators.
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