| 1. |
- Penolazzi, Sandro, et al.
(författare)
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A General Approach to High-Level Energy and Performance Estimation in SoCs
- 2009
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Ingår i: 22ND INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH 8TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS. - 9780769535067 ; , s. 200-205
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Konferensbidrag (refereegranskat)abstract
- We present a high-level methodology for efficient and accurate estimation of energy and performance in SoCs at Functional Untimed Level. We then validate the proposed method against gate level for accuracy and against TLM-PV for speed. We show that the method is within 15% of gate-level accuracy and in aver-age 28x faster than TLM-PV, for the benchmark applications selected.
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| 2. |
- Penolazzi, Sandro, et al.
(författare)
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A general approach to high-level energy and performance estimation in system-on-chip architectures
- 2009
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Ingår i: Journal of Low Power Electronics. - : American Scientific Publishers. - 1546-1998. ; 5:3, s. 373-384
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Tidskriftsartikel (refereegranskat)abstract
- We present a high-level methodology for efficient and accurate estimation of energy and performance in SoCs. Differently from the most common approaches, which rely on Transaction-Level Modeling (TLM), we infer energy and performance figures directly from the Functional Untimed Level, by running the algorithmic specification natively on a common host machine. We then validate the proposed method against gate level for accuracy and against TLM-PV for speed. We show that the method is within 17% of gate-level accuracy and in average 28x faster than TLM-PV, for the benchmark applications selected.
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| 3. |
- Penolazzi, Sandro, et al.
(författare)
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A layered approach to estimating power consumption
- 2006
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Ingår i: 24th Norchip Conference, Proceedings. - : IEEE. - 9781424407729 ; , s. 93-98
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Konferensbidrag (refereegranskat)abstract
- A layered approach to estimating power consumption at the highest level of abstraction is presented. This approach is sufficiently accurate and fast enough to be used as guide for exploring the algorithmic and architectural space. The layers span from use-case level down to gate level. Speed and accuracy come from our ability to relate parameterized transactions at architectural level to switching activity at gate level and to perform architecturally-aware application-level simulation for specific or sweeps of use-cases. That enables us to recreate accurately architectural-level transactions. Additionally, we use preliminary floorplan to factor physical design aspects to improve the accuracy of our estimates. We base our work on the industry standard SPIRIT for specifying IPs and Platforms. Early results of work are also presented.
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| 5. |
- Penolazzi, Sandro
(författare)
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A System-Level Framework for Energy and Performance Estimation in System-on-Chip Architectures
- 2011
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Shifting the design entry point up to the system level is the most important countermeasure adopted to manage the increasing complexity of SoCs. The reason is that decisions taken at this level, early in the design cycle, have the greatest impact on the final design in terms of performance, energy efficiency and silicon area occupation. However, taking decisions at this level is very difficult, since the design space is extremely wide, and it has so far been mostly a manual activity. Efficient system-level estimation tools are therefore necessary to enable proper design-space exploration and the development of system-level synthesis tools. Proposing an efficient approach to system-level estimation is the main contribution of this thesis. The approach consists of three layers. The bottom layer relies on building a library of IP energy and performance models, where each IP functionality is pre-characterized. Characterization is done only once at the gate level, which gives high accuracy to the approach. The implementation of an energy and performance model for a Leon3 processor is reported as an example. The impact that the IP-to-IP communication infrastructure has over individual IP properties is also taken into account, for bus-based and NoC-based architectures. The intermediate layer is where the actual estimation takes place. At this level, applications are run and profiled on a development host (a common PC). This allows us to create a trace of the executed source code, which is then mapped to the assembly code of the target architecture. This operation allows a trace of target instructions to be indirectly built and confers high speed on the whole methodology. Once the target trace is inferred, energy and performance figures can be extracted by using the IP models from the bottom layer. To make the whole process possible, changes are made to the GNU GCC compiler. Estimation is shown for a few common image/video codec applications. The top layer is a refinement layer that accounts for the presence of caches and for the fact that multiple applications normally run concurrently, share the same resources and are controlled by an operating system. Statistical models are built to account for the impact of each of these components. An MPSoC hosting up to 15 processors and using both fixed-priority and round robin bus arbitration is used for modeling bus contention. The RTEMS operating system is taken as a reference to model the OS impact. Validation for each layer is also carried out. The results show that the approach is within 15% of gate-level accuracy and exhibits an average speed-up of 30X compared to transaction-level modeling (TLM).
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| 6. |
- Penolazzi, Sandro, et al.
(författare)
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Energy and Performance Model of a SPARC Leon3 Processor
- 2009
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Ingår i: PROCEEDINGS OF THE 2009 12TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, ARCHITECTURES, METHODS AND TOOLS. - LOS ALAMITOS : IEEE COMPUTER SOC. - 9780769537825 ; , s. 651-656
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Konferensbidrag (refereegranskat)abstract
- We present a general methodology to implement a processor energy model, based on instruction-level characterization, and we apply it to a SPARC-based Leon3 processor. The model is characterized by simulating back-annotated gate-level netlist and has two levels of accuracy: a coarse-grain estimation based on characterizing each single instruction and a fine-grain estimation accounting for the impact of instructions interdependency on energy and based on characterizing pairs of instructions together. Our investigation also keeps into account the effect that both data switching activity and registers correlation have on energy. We validate our model by applying it to a set of instruction traces generated by Instruction Set Simulation and compare it to extracting energy directly from gate level. We achieve a worst-case error similar or equal to 12% and a speedup higher than 1000 times.
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