| 1. |
- Anwar, Hassan, et al.
(författare)
-
Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures
- 2014
-
Ingår i: ACM International Conference Proceeding Series. - New York, NY, USA : ACM. - 9781450328227 ; , s. 64-67
-
Konferensbidrag (refereegranskat)abstract
- Today, reconfigurable architectures are becoming increas- ingly popular as the candidate platforms for neural net- works. Existing works, that map neural networks on re- configurable architectures, only address either FPGAs or Networks-on-chip, without any reference to the Coarse-Grain Reconfigurable Architectures (CGRAs). In this paper we investigate the overheads imposed by implementing spiking neural networks on a Coarse Grained Reconfigurable Ar- chitecture (CGRAs). Experimental results (using point to point connectivity) reveal that up to 1000 neurons can be connected, with an average response time of 4.4 msec.
|
|
| 2. |
|
|
| 3. |
- Ellervee, Peeter, et al.
(författare)
-
Exploring ASIC Design Space at System Level with a Neural Network Estimator
- 1994
-
Ingår i: Proc. of IEEE ASIC-conference, 1994.
-
Konferensbidrag (refereegranskat)abstract
- Estimators are critical tools in doing architectural level exploration of the design space. We present a novel approach to estimation based on the multilayer perceptron which builds the estimation function during the learning process and thus allows to describe arbitrary complex functions. We also describe how the control data flow graph is encoded for the neural network input and we present results of the first experiments made with realistic design examples.
|
|
| 4. |
- Hellberg, Lars, et al.
(författare)
-
System oriented VLSI curriculum at KTH
- 1997
-
Ingår i: ; , s. 57-59
-
Konferensbidrag (refereegranskat)abstract
- This paper describes the restructuring of VLSI education at the Royal Institute of Technology (KTH). Changing needs of industry, advances in technology and design methodology has required a significant reorganization of VLSI education with combined emphasis on system issues and associated physical constraints. We present here a course structure which will address, in parallel fashion, the key design issues for future system products
|
|
| 5. |
- Hemani, Ahmed, et al.
(författare)
-
A structure of modern VLSI curriculum
- 1994
-
Ingår i: ; , s. 204-208
-
Konferensbidrag (refereegranskat)abstract
- This paper describes the restructuring of VLSI education at Royal Institute of Technology, Sweden. Changing needs of industry, advances in technology and design methodology has required a significant reorganisation of VLSI education with emphasis on system issues. This restructuring is not viewed as a one step process, rather as a continuous process including close interaction between education and research
|
|
| 6. |
|
|
| 7. |
- Hemani, Ahmed, et al.
(författare)
-
High-level synthesis of control and memory intensive communication systems
- 1995
-
Ingår i: ; , s. 185-191
-
Konferensbidrag (refereegranskat)abstract
- Communication sub-systems that deal with switching, routing and protocol implementation often have their functionality dominated by control logic and interaction with memory. Synthesis of such Control and Memory Intensive Systems (hereafter abbreviated to CMISTs) poses demands that in the past have not been met satisfactorily by general purpose high-level synthesis (HLS) tools and have led to several research efforts to address these demands. In this paper we: characterise CMISTs from the synthesis viewpoint; present a synthesis methodology adapted for CMISTs; present the Operation and Maintenance (OAM) Protocol of the ATM, its modelling in VHDL and synthesis aspects of the VHDL model; present the results of applying the synthesis methodology to the OAM as a test case-the results are compared to that obtained using the not adapted general purpose High-level synthesis tool; prove the efficacy of the proposed synthesis methodology by applying it to an industrial design and comparing our results to the results from two commercial HLS tools and to the results obtained by designing manually at register-transfer level
|
|
| 8. |
|
|
| 9. |
|
|
| 10. |
- Isoaho, Jouni, et al.
(författare)
-
High level synthesis in DSP ASIC optimization
- 1994
-
Ingår i: Proc. of 7th IEEE ASIC Conference and Exhibit. ; , s. 75-78
-
Konferensbidrag (refereegranskat)abstract
- In this paper Digital Signal Processing (DSP) system optimization with High Level Synthesis (HLS) environment is presented. To optimize a behavioural VHDL description, commercial SYNT and Synopsys synthesis tools are utilized. The optimization results are improved with a simple rule based preallocator. The coefficient optimization is done in Matlab to provide an efficient implementation of power-of-two and multiply-accumulate based FIR filters. The optimization results are presented using practical filter examples
|
|
