| 1. |
- Ingelsson, Urban, et al.
(författare)
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Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption
- 2015
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Ingår i: IEEE Transactions on Computers. - 0018-9340. ; 64:12, s. 3335-3347
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Tidskriftsartikel (refereegranskat)abstract
- System-on-chips (SOCs) and 3D stacked ICs are often tested for manufacturing defects in a modular fashion, enabling us to record the module test pass probability. We use this pass probability to exploit the abort-on-fail feature of automatic test equipment (ATE) and hence reduce the expected test time in the context of single-site testing. We present a model for calculation of expected test time, for which the abortable test unit can be a module test, a test pattern or a clock cycle. Given an SOC, with test architecture consisting of module test wrappers and test access mechanisms (TAMs), and given module test pass probabilities, we schedule the tests on each TAM to minimize the expected test time. We describe four scheduling heuristics, one without and three with preemption. Experimental results for the ITC’02 SOC Test Benchmarks show 3.5% and 20% reduction of expected test time in SOCs with 0.89 and 0.71 SOC test pass probability respectively, without modification of SOC or ATE. Further experiments show how accurate estimates for the module test pass probability or the distribution of pass probability over test patterns need to be to lead to effective test schedulng.
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| 2. |
- Ingelsson, Urban, et al.
(författare)
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Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
- 2005
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Ingår i: IEEE European Test Symposium ETS 05,2005. - Tallinn, Estonia : IEEE Computer Society Press.
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Konferensbidrag (refereegranskat)abstract
- Complex SOCs are increasingly tested in a modular fashion, which enables us to record the yield-per-module. In this paper, we consider the yield-per-module as the pass probability of the module s manufacturing test. We use it to exploit the abort-on-fail feature of ATEs, in order to reduce the expected test application time. We present a model for expected test application time, which obtains increasing accuracy due to decreasing granularity of the abortable test unit. For a given SOC, with a modular test architecture consisting of wrappers and disjunct TAMs, and for given pass probabilities per module test, we schedule the tests on each TAM such that the expected test application time is minimized. We describe two heuristic scheduling approaches, one without and one with preemption. Experimental results for the ITC 02 SOC Test Benchmarks demonstrate the effectiveness of our approach, as we achieve up to 97% reduction in the expected test application time, without any modification to the SOC or ATE.
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| 3. |
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| 4. |
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| 5. |
- Ghani Zadegan, Farrokh, et al.
(författare)
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Access Time Analysis for IEEE P1687
- 2012
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Ingår i: IEEE Transactions on Computers. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9340 .- 1557-9956. ; 61:10, s. 1459-1472
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Tidskriftsartikel (refereegranskat)abstract
- The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between the IEEE Standard 1149.1 test access port (TAP) and on-chip embedded test, debug and monitoring logic (instruments), such as scan chains and temperature sensors. A key feature in P1687 is to include Segment Insertion Bits (SIBs) in the scan path to allow flexibility both in designing the instrument access network and in scheduling the access to instruments. This paper presents algorithms to compute the overall access time (OAT) for a given P1687 network. The algorithms are based on analysis for flat and hierarchical network architectures, considering two access schedules, i.e., concurrent schedule and sequential schedule. In the analysis, two types of overhead are identified, i.e., network configuration data overhead and JTAG protocol overhead. The algorithms are implemented and employed in a parametric analysis and in experiments on realistic industrial designs.
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| 6. |
- Ghani Zadegan, Farrokh, et al.
(författare)
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Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687
- 2012
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Ingår i: IEEE Design & Test of Computers. - : IEEE. - 0740-7475 .- 1558-1918. ; 29:2, s. 79-88
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Tidskriftsartikel (refereegranskat)abstract
- Modern chips may contain a large number of embedded test, debugging, configuration, and monitoring features, called instruments. An instrument and its instrument access procedures may be pre-developed and reused, and each instrument—in different chips and through the life-time of a chip—may be accessed in different ways, which requires retargeting. To address reuse and retargeting of instrument access procedures, IEEE P1678 specifies a hardware architecture, a hardware description language, and an access procedure description language. In this paper, we investigate how P1687 facilitates instrument access procedure reuse and retargeting.
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| 7. |
- Ingelsson, Urban, et al.
(författare)
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Cost Reduction of Wear-Out Monitoring by Measurement Point Selection
- 2011
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Ingår i: <em>The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011</em>.
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Early failure rates have increased due to reduced feature dimensions and electromigration wear-out. Periodic delay measurements can be employed to estimate the state of wear-out. Including delay measurement sensors on-chip is costly. Therefore, a method is proposed to reduce the number of measurement points. The method identi?es wear-out sensitive interconnects and selects a small number of measurement points to target the identi?ed interconnects. The method is demonstrated on ISCAS85 benchmark ICs.
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| 8. |
- Ingelsson, Urban, et al.
(författare)
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Measurement Point Selection for In-Operation Wear-Out Monitoring
- 2011
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Ingår i: 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS11), Cottbus, Germany, April 13-15, 2011.. - : IEEE. - 9781424497553 ; , s. 381-386
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Konferensbidrag (refereegranskat)abstract
- In recent IC designs, the risk of early failure due to electromigration wear-out has increased due to reduced feature dimensions. To give a warning of impending failure, wearout monitoring approaches have included delay measurement circuitry on-chip. Due to the high cost of delay measurement circuitry this paper presents a method to reduce the number of necessary measurement points. The proposed method is based on identification of wear-out sensitive interconnects and selects a small number of measurement points that can be used to observe the state of all the wear-out sensitive interconnects. The method is demonstrated on ISCAS85 benchmark ICs with encouraging results.
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| 9. |
- Larsson, Anders, et al.
(författare)
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Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs
- 2010
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Ingår i: Design and Test Technology for Dependable Systems-on-chip. - : Information Science Publishing. - 1609602129 - 9781609602123
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Bokkapitel (övrigt vetenskapligt/konstnärligt)abstract
- Designing reliable and dependable embedded systems has become increasingly important as the failure of these systems in an automotive, aerospace or nuclear application can have serious consequences.Design and Test Technology for Dependable Systems-on-Chip covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC). This book provides insight into refined "classical" design and test topics and solutions for IC test technology and fault-tolerant systems.
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| 10. |
- Larsson, Erik, et al.
(författare)
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Test scheduling on IJTAG
- 2010
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Ingår i: Nordic Test Forum (NTF 2010), Drammen, Norway..
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Konferensbidrag (refereegranskat)
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