| 1. |
- Sköldstrom, Pontus, et al.
(författare)
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Towards unified programmability of cloud and carrier infrastructure
- 2014
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Ingår i: Proceedings - 2014 3rd European Workshop on Software-Defined Networks, EWSDN 2014. - 9781479969197 ; , s. 55-60
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Konferensbidrag (refereegranskat)abstract
- The rise of cloud services poses considerable challenges on the control of both cloud and carrier network infrastructures. While traditional telecom network services rely on rather static processes (often involving manual steps), the wide adoption of mobile devices including tablets, smartphones and wearables introduce previously unseen dynamics in the creation, scaling and withdrawal of new services. These phenomena require optimal flexibility in the characterization of services, as well as on the control and orchestration of both carrier and cloud infrastructure. This paper proposes a unified programmability framework addressing: the unification of network and cloud resources, the integrated control and management of cloud and network, the description for programming networked/cloud services, and the provisioning processes of these services. In addition proofs-of-concept are provided based on existing open source control software components. © 2014 IEEE.
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| 2. |
- Widdowson, A., et al.
(författare)
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Experience of handling beryllium, tritium and activated components from JET ITER like wall
- 2016
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Ingår i: Physica Scripta. - : Institute of Physics Publishing (IOPP). ; T167
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Konferensbidrag (refereegranskat)abstract
- JET components are removed periodically for surface analysis to assess material migration and fuel retention. This paper describes issues related to handling JET components and procedures for preparing samples for analysis; in particular a newly developed procedure for cutting beryllium tiles is presented. Consideration is also given to the hazards likely due to increased tritium inventory and material activation from 14 MeV neutrons following the planned TT and DT operations (DTE2) in 2017. Conclusions are drawn as to the feasibility of handling components from JET post DTE2.
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| 3. |
- Josefson, Lennart, 1954, et al.
(författare)
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Simplified FEA models in the analysis of the redistribution of beneficial compressive stresses in welds during cyclic loading
- 2018
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Ingår i: Proceedings of the International Conference on Offshore Mechanics and Arctic Engineering - OMAE. ; 11B
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Konferensbidrag (refereegranskat)abstract
- The fatigue life of welded joints can be improved by modifying the weld toe geometry or by inducing beneficial compressive residual stresses in the weld. However, in the second case, the induced compressive residual stresses may relax when the welded joint is subjected to cyclic loading containing high tensile or compressive stress peaks. The stability of induced compressive stresses is investigated for a longitudinal gusset made of a S355 steel. Two methods are considered; either carrying out a high frequency mechanical impact (HFMI) treatment after welding or alternatively using low transformation temperature (LTT) electrodes during welding. The specimen is then subjected to a cyclic loading case with one cycle with a tensile peak (with magnitude reaching the local yield stress level) followed by cycles with constant amplitude. A sequential finite element analysis (FEA) is performed thereby preserving the history of the elasto-plastic behavior. Both the welding process and the HFMI treatment are simulated using simplified approaches, i.e., the welding process is simulated by applying a simplified thermal cycle while the HFMI treatment is simulated by a quasi-static contact analysis. It is shown that using the simplified approaches to modelling both the welding process and HFMI treatment gives results that correlate qualitatively well with the experimental and FEA data available in the literature. Thus, for comparison purposes, simplified models may be sufficient. Both the use of the HFMI treatment and LTT electrodes give approximately the same compressive stress at the weld toe but the extent of the compressive stress zone is deeper for HFMI case. During cyclic loading it is shown that the beneficial effect of both methods will be substantially reduced if the test specimen is subjected to unexpected peak loads. For the chosen load sequence, with the same maximum local stress at the weld toe, the differences in stress curves of the HFMI-treated specimen and that with LTT electrodes remain. While the LTT electrode gives the lowest (compressive) stress right at the well toe, it is shown that the overall effect of the HFMI treatment is more beneficial.
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| 6. |
- Aamir, Syed Ahmed, 1980-, et al.
(författare)
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A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-nm CMOS
- 2010
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Ingår i: Proceedings of the 17th IEEE International Conference on Electronics, Circuits, and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). ; , s. 29-32
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Konferensbidrag (refereegranskat)abstract
- In this work, we describe the implementation of a 1. 2-V pseudo-differential operational transconductance amplifier (OTA) with common-mode feedforward (CMFF) and inherent common-mode feedback (CMFB) in a 65-nm, digital CMOS process. The OTA architecture provides an inherent CMFB when cascaded OTA structures are utilized andthis work has studied a cascaded amplifier consisting of fourstages. Due to the low-gain using core 65-nm circuit devices, the overall gain must be distributed on all four stages to acquire a gain of more than 60 dB, while maintaining a-3-dB bandwidth of 200 MHz. To achieve high gain, we propose using a modified, positive-feedback, cross-coupled input differential stage. The modified OTA achieves a high output swing of ± 0.85 V due to only two stacked transistors, 88 dB DC gain and a third-order harmonic of -60 dB for 800 mVpp at 30 MHz. Further on, in a capacitive buffer configuration, we achieve a high slew rate of 1240 V/µS, -3-dB bandwidth of 509 MHz, signal-to-noise ratio of 63 dB while consuming 10.4 mW power.
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| 7. |
- Aamir, Syed Ahmed, 1980-, et al.
(författare)
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A 500-MHz low-voltage programmable gain amplifier for HD video in 65-nm CMOS
- 2010
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Ingår i: Proceedings of 28th IEEE Norchip Conference., NORCHIP'10. - Tampere : www.ieee.org. - 9781424489718 - 9781424489725 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- This work describes the implementation of a 1.2-V programmable gain amplifier (PGA) for high-definition (HD) video digitizers in a 65-nm digital CMOS process. The “pseudo” switched-capacitor (SC) PGA architecture buffers the video signal, without switching, during the active video. The SC circuitry is used for setup of DC operating point during horizontal and vertical blanking periods. Additionally, it compensates for the `sync-tip' of analog video signals to an equal blanking level for increased dynamic range to the digitizer following the PGA. The operational transconductance amplifier (OTA) employed as main amplifier in the PGA is a pseudo-differential, positive-feedback input stage architecture with a common-mode feedforward (CMFF) technique. The common-mode feedback (CMFB) is provided once two OTAs are cascaded. Schematic-level simulation results show that the OTA maintains a -3-dB bandwidth of 550 MHz, while keeping the distortion HD3 at -60 dB for a 30-MHz, 850 mVpp high definition video signal. The 88 dB DC gain is distributed among four OTA stages and the overall, combined PGA achieves a signal-to-noise ratio of 63 dB. Due to only two stacked transistors, it achieves high output swing of ±0.85 V, 1240 V/μs slew rate while consuming 10.4 mW power.
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| 8. |
- Afzal, Nadeem, et al.
(författare)
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Power efficient arrangement of oversampling sigma-delta DAC
- 2012
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Ingår i: NORCHIP, 2012. - : IEEE. - 9781467322218 - 9781467322225 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- A hardware efficient arrangement of digital-to-analog conversion blocks is presented by segmenting digital-to-analog converter (DAC). This segmenting of DAC is done by using buss-split design of digital sigma-delta modulator (DSDM). The reduction in the word length of input to both DSDM and DAC is analyzed with respect to performance because the input word length decides the complexity of these components. We show that effective performance can be achieved from the presented hardware efficient arrangement. All conclusions are drawn based on theory and simulations.
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| 9. |
- Ahmed Aamir, Syed, et al.
(författare)
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Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers
- 2013
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Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS), 2013. - : IEEE conference proceedings. - 9781467357609 ; , s. 381-384
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Konferensbidrag (refereegranskat)abstract
- This paper presents the frequency compensation of high-speed, low-voltage multistage amplifiers. Two frequency compensation techniques, the Nested Miller Compensation with Nulling Resistors (NMCNR) and Reversed Nested Indirect Compensation (RNIC), are discussed and employed on two multistage amplifier architectures. A four-stage pseudo-differential amplifier with CMFF and CMFB is designed in a 1.2 V, 65-nm CMOS process. With NMCNR, it achieves a phase margin (PM) of 59° with a DC gain of 75 dB and unity-gain frequency (fug) of 712 MHz. With RNIC, the same four-stage amplifier achieves a phase margin of 84°, DC gain of 76 dB and fug of 2 GHz. Further, a three-stage single-ended amplifier is designed in a 1.1-V, 40-nm CMOS process. The three-stage OTA with RNIC achieves PM of 81°, DC gain of 80 dB and fug of 770 MHz. The same OTA achieves PM of 59° with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages.
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| 10. |
- Alvbrant, Joakim, 1973-, et al.
(författare)
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Study and Simulation Example of a Redundant FIR Filter
- 2012
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Ingår i: Proceedings 30th Norchip Conference. - : IEEE. - 9781467322225 - 9781467322218 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- In this paper we present a study and simulation results of the structure and design of a redundant finite-impulse response (FIR) filter. The filter has been selected as an illustrative example for biologically-inspired circuits, but the structure can be generalized to cover other signal processing systems. In the presented study, we elaborate on signal processing properties of the filter if we apply a redundant architecture were different computing paths can be utilized. An option is to utilize different computing paths as inspired by biological architectures (BIAs). We present typical simulation results for a low-pass filter illustrating the trade-offs and costs associated with this architecture.
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