| 1. |
- Forsberg, Håkan, et al.
(författare)
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Radar signal processing using pipelined optical hypercube interconnects
- 2001
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Ingår i: Proceedings of the 15th International Parallel and Distributed Processing Symposium. - Los Alamitos, California : IEEE Computer Society Press. - 0769509908 ; , s. 2043-2052
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Konferensbidrag (refereegranskat)abstract
- In this paper, we consider the mapping of two radar algorithms on a new scalable hardware architecture. The architecture consists of several computational modules that work independently and send data simultaneously in order to achieve high throughput. Each computational module is composed of multiple processors connected in a hypercube topology to meet scalability and high bisection bandwidth requirements. Free-space optical interconnects and planar packaging technology make it possible to transform the hypercubes into planes. Optical fan-out reduces the number of optical transmitters and thus the hardware cost. Two example systems are analyzed and mapped onto the architecture. One 64-channel airborne radar system with a sustained computational load of more than 1.6 TFLOPS, and one ground-based 128-channel radar system with extreme inter-processor communication demands.
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| 2. |
- Hoang, Hoai, et al.
(författare)
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Deadline first scheduling in switched real-time Ethernet - deadline partitioning issues and software implementation experiments
- 2002
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Ingår i: Euromicro RTS 2002. - Los Alamitos, Calif. : IEEE Computer Society. - 0769516653 - 9780769516653 - 076951667X - 9780769516677 ; , s. 68-71
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Konferensbidrag (refereegranskat)abstract
- This paper presents work on a switched Ethernet network extended to allow for earliest deadline first (EDF) scheduling. We show by example that asymmetric deadline partitioning between the links of a real-time channel can increase the utilization substantially, still not violating the real-time guarantees. We also report measurements on a software implementation of the switch on an ordinary PC.
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| 3. |
- Hoang, Hoai, et al.
(författare)
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Switched real-time Ethernet with earliest deadline first scheduling - protocols and traffic handling
- 2002
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Ingår i: Proceedings. - Los Alamitos, Calif. : IEEE Computer Society. - 0769515738 - 9780769515731 - 0769515746 - 9780769515748 - 0769515754 - 9780769515755 ; 5:1, s. 105-115
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Konferensbidrag (refereegranskat)abstract
- There is a strong interest of using the cheap and simple Ethernet technology for industrial and embedded systems. This far, however, the lack of real-time services has prevented this change of used network technology. This paper presents enhancements to full-duplex switched Ethernet for the ability of giving throughput and delay guarantees. The switch and the end-nodes controls the real-time traffic with Earliest Deadline First (EDF) scheduling on the frame level. No modification to the Ethernet standard is needed in the network that supports both real-time and non-real-time TCP/IP communication. The switch is responsible for admission control where feasibility analysis is made for each link between source and destination. The switch broadcasts Ethernet frames regularly to clock synchronize the end nodes and to implement flow control for non-real-time traffic.
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| 4. |
- Jonsson, Magnus, 1969-, et al.
(författare)
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Fiber-ribbon pipeline ring network for high-performance distributed computing systems
- 1997
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Ingår i: Proceedings of the Third International Symposium on Parallel Architectures, Algorithms, and Networks, 1997. (I-SPAN '97). - : IEEE. ; , s. 138-143
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Konferensbidrag (refereegranskat)abstract
- In this paper, we propose a high-bandwidth ring network built up with fiber-ribbon point-to-point links. The network has support for both packet switched and circuit switched traffic. Very high throughputs can be achieved in the network due to pipelining, i.e., several packets can be traveling through the network simultaneously but in different segments of the ring. The network can be built today using fiber-optic off-the-shelf components. The increasingly good price/performance ratio for fiber-ribbon links indicates a great success potential for the proposed kind of networks. We also present a massively parallel radar signal processing system with exceptionally high demands on the communication network. An aggregated throughput of tens of Gb/s is needed in this application, and this is achieved with the proposed network.
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| 5. |
- Jonsson, Magnus, 1969-, et al.
(författare)
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Time-deterministic WDM star network for massively parallel computing in radar systems
- 1996
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Ingår i: Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections. - Los Alamitos, California : IEEE Computer Society Press. - 0818675918 ; , s. 85-93
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Konferensbidrag (refereegranskat)abstract
- In massively parallel computer systems for embedded real-time applications there are normally very high bandwidth demands on the interconnection network. Other important properties are time-deterministic latency and services to guarantee that deadlines are met. In this paper we analyze how these properties vary with the design parameters for a passive optical star network, specifically when used in a massively parallel radar signal processing system. The aggregated bandwidth and computational power of the radar system are approximately 45 Gb/s and 100 GOPS, respectively. The analysis is focused on the medium access control protocol, called TD-TWDMA, for the time and wavelength multiplexed network. It is concluded that the proposed network is very well suited to this kind of signal-processing applications. We also present a new distributed slot-allocation algorithm with real-time properties.
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| 6. |
- Mors, Niklas, et al.
(författare)
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A Ethernet based Metropolitan Area Open Access Architecture
- 2003
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Ingår i: IASTED International Multi-Conference on Applied Informatics. - : IASTED/ACTA Press. - 0889863415 ; , s. 571-576
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Konferensbidrag (populärvet., debatt m.m.)abstract
- Quality of Service (QoS) has become increasingly important in metropolitan area networks and even more important in open access networks where service providers should be able to offer their services on equal terms. This paper present a network architecture with a hierarchical star-mesh topology, which provides the scalability and redundancy required for future open access networks. To support QoS a combination of Ethernet and Multiprotocol Label Switching (MPLS) is proposed. With the use of a switch, on the highest level, based on micro electromechanical system (MEMS) technology this proposed architecture could reach aggregated bitrates above 10 Tbit/s. IPSec is proposed for solving the security issues in the network that emerges when different service providers share the same network and future applications are developed.
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| 7. |
- Pelliccione, Patrizio, 1975, et al.
(författare)
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Architecting cars as constituents of a system of systems
- 2016
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Ingår i: ACM International Conference Proceeding Series. - New York, NY, USA : Association for Computing Machinery (ACM). - 9781450363990 ; , s. 1-7
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Konferensbidrag (refereegranskat)abstract
- Future transportation systems will be a heterogeneous mix of items with varying connectivity and interoperability. A mix of new technologies and legacy systems will co-exist to realize a variety of scenarios involving not only connected cars but also road infrastructures, pedestrians, cyclists, etc. Future transportation systems can be seen as a System of Systems (SoS), where each constituent system - one of the units that compose an SoS - can act as a standalone system, but the cooperation among the constituent systems enables new emerging and promising scenarios. In this paper we investigate how to architect cars so that they can be constituents of future transportation systems. This work is realized in the context of two Swedish projects coordinated by Volvo Cars and involving some universities and research centers in Sweden and many suppliers of the OEM, including Autoliv, Arccore, Combitech, Cybercom, Knowit, Prevas, ÅF-Technology, Semcom, and Qamcom.
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| 8. |
- Taveniku, Mikael, et al.
(författare)
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A multiple SIMD mesh architecture for multi-channel radar processing
- 1996
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Ingår i: Proceedings of: ICSPAT'96, international conference on signal processing applications & technology, Boston MA, USA, October 7-10. - : Miller Freeman. ; , s. 1421-1427
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Konferensbidrag (refereegranskat)abstract
- In modern and future radar applications there are high demands on the signal processing chain in terms of computational power and generality. At the same time, there are hard size and power consumption constraints. This paper reports on a project whose aim is to find a good scalable computer architecture that is flexible, programmable and as general-purpose as possible without too much performance loss.The proposed architecture consists of multiple SIMD computing modules, each based on a number of small mesh arrays. The modules are fully programmable and work globally as a MIMD machine and locally as SIMD machines. The data network is modular and provides both high bandwidth capacity and fast response. It has a fiber-optic stars topology, and employs time and wavelength division multiplexing, together with a medium access method specially developed for real-time systems.In this paper, we use a radar system with 64 processing channels to illustrate the algorithms and the usage of the processor modules. We show that it is possible to use a machine, consisting of small mesh processor arrays forming larger modules, with good efficiency. The building blocks show good balance between computational power and I/O bandwidth, and the SIMD approach seems good from algorithm-mapping point of view.
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| 9. |
- Taveniku, Mikael, et al.
(författare)
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The VEGA moderately parallel MIMD, moderately parallel SIMD, architecture for high performance array signal processing
- 1998
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Ingår i: Proceedings of the first merged International Parallel Processing Symposium & Symposium on Parallel and Distributed Processing. - Los Alamitos, Calif. : IEEE Computer Press. ; , s. 226-232
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Konferensbidrag (refereegranskat)abstract
- In array radar signal processing applications, the processing demands range from tens of GFLOPS to several TFLOPS. To address this, as well as the, size and power dissipation issues, a special purpose “array signal processing” architecture is proposed. We argue that a combined MIMD-SIMD system can give flexibility, scalability, and programmability as well as high computing density. The MIMD system level, where SIMD modules are interconnected by a fiber-optic real-time network, provides the high level flexibility while the SIMD module level provides the compute density. In this paper we evaluate different design alternatives and show how the VEGA architecture was derived. By examining the applications and the algorithms used, the SIMD mesh processor is found be sufficient. However, the smaller the meshes are the better is the flexibility and efficiency. Then, based on prototype VLSI implementations and on instruction statistics, we find that a relatively large pipelined processing element maximises the performance per area. It is thereby concluded that the small SIMD mesh processor array with powerful processing elements is the best choice. These observations are further exploited in the design of the single-chip SIMD processor array to be included in the MIMD-style overall system. The system scales from 6.4 GFLOPS to several TFLOPS peak performance.
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