| 1. |
- Candaele, Bernard, et al.
(författare)
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Mapping Optimisation for Scalable multi-core ARchiTecture : The MOSART approach
- 2010
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Ingår i: Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010. - 9780769540764 ; , s. 518-523
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Konferensbidrag (refereegranskat)abstract
- The project will address two main challenges of prevailing architectures: 1) The global Interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures Including middleware services and a run-time data manager for NoC based communication infrastructure; 2) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.
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| 2. |
- Candaele, Bernard, et al.
(författare)
-
The MOSART Mapping Optimization for multi-core Architectures
- 2011
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Ingår i: VLSI 2010 Annual Symposium. - Dordrecht : Springer Publishing Company. ; , s. 181-195
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Konferensbidrag (refereegranskat)abstract
- MOSART project addresses two main challenges of prevailing architectures: (i) Theglobal interconnect and memory bottleneck due to a single, globally shared memorywith high access times and power consumption; (ii) The difficulties in programmingheterogeneous, multi-core platforms MOSART aims to overcome these through amulti-core architecture with distributed memory organization, a Network-on-Chip(NoC) communication backbone and configurable processing cores that are scaled,optimized and customized together to achieve diverse energy, performance, cost andsize requirements of different classes of applications. MOSART achieves this by:(i) Providing platform support for management of abstract data structures includingmiddleware services and a run-time data manager for NoC based communicationinfrastructure; (ii) Developing tool support for parallelizing and mapping applicationson the multi-core target platform and customizing the processing cores for theapplication.
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| 3. |
- Kreku, Jari, et al.
(författare)
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SystemC Work load Model Generation from UML for Performance Simulation
- 2007
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Ingår i: Proceedings of the International Conference Forum on Specification and Design Languages (FDL) 2007.
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Konferensbidrag (refereegranskat)abstract
- An extension to workload-based performance simulation approach is presented, which enables modelling applications using a UML tool and transforming them to SystemC with a code generator. Therefore partial reuse of existing UML application models is feasible, removing the need for separate workload modelling in SystemC. The UML to SystemC transformation is applied to a mobile video player case study to gain experience on the strengths and weaknesses of the method.
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| 4. |
- Soininen, Juha-Pekka, et al.
(författare)
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Extending Platform-Based Design to Network on Chip Systems
- 2003
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Ingår i: Proceedings of the International Conference on VLSI Design.
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Konferensbidrag (refereegranskat)abstract
- Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been proposed as backbones for billion-transistor ASICs. We present a novel layered backbone-platform-system (BPS) design methodology for development of network-on-chip based products. It combines and extends the distributed, parallel, embedded and platform-based design concepts in order to manage the diversity and complexity of NOCbased-systems. The reuse of communication principles in various platforms, the reuse of platforms in product differentiation, and system-level decision-support methods are the cornerstones of our methodology. The presented mappability estimation and workload simulations demonstrate the feasibility of such methods.
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