| 1. |
- Ohlsson, Lars, et al.
(författare)
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First InGaAs lateral nanowire MOSFET RF noise measurements and model
- 2017
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Ingår i: 75th Annual Device Research Conference, DRC 2017. - 9781509063277
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Konferensbidrag (refereegranskat)abstract
- The first radio frequency (RF) noise measurements on lateral nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs) and a noise model are presented. We have characterized the RF noise and scattering parameters of an indium gallium arsenide (InGaAs) device. A fitted model yields extrapolated ft = 316 GHz current gain cutoff and fmax = 166 GHz maximum oscillation frequency. This device technology is being developed for millimeter wave circuit implementations, targeting a 94 GHz carrier frequency. The modeled intrinsic Fmin < 1dB minimum noise figure obtained promises performance at the target band, given reduction of gate parasitics. In any wireless system, noise and bandwidth limits the performance. Understanding of RF noise in nanowire MOSFET devices is thereby key for realization of future radar and communications systems.
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| 2. |
- Babadi, Aein S., et al.
(författare)
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Impact of doping and diameter on the electrical properties of GaSb nanowires
- 2017
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Ingår i: Applied Physics Letters. - : AIP Publishing. - 0003-6951 .- 1077-3118. ; 110:5
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Tidskriftsartikel (refereegranskat)abstract
- The effect of doping and diameter on the electrical properties of vapor-liquid-solid grown GaSb nanowires was characterized using long channel back-gated lateral transistors and top-gated devices. The measurements showed that increasing the doping concentration significantly increases the conductivity while reducing the control over the channel potential and shifting the threshold voltage, as expected. The highest average mobility was 85 cm2/V·s measured for an unintentionally doped GaSb nanowire with a diameter of 45 nm, whereas medium doped nanowires with large diameters (81 nm) showed a value of 153 cm2/V·s. The mobility is found to be independent of nanowire diameter in the range of 36 nm-68 nm, while the resistivity is strongly reduced with increasing diameter attributed to the surface depletion of charge carriers. The data are in good agreement with an analytical calculation of the depletion depth. A high transconductance was achieved by scaling down the channel length to 200 nm, reaching a maximum value of 80 μS/μm for a top-gated GaSb nanowires transistor with an ON-resistance of 26 kΩ corresponding to 3.9 Ω.mm. The lowest contact resistance obtained was 0.35 Ω·mm for transistors with the highest doping concentration.
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| 3. |
- Berg, Martin, et al.
(författare)
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A transmission line method for evaluation of vertical InAs nanowire contacts
- 2015
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Ingår i: Applied Physics Letters. - : AIP Publishing. - 0003-6951 .- 1077-3118. ; 107:23
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we present a method for metal contact characterization to vertical semiconductor nanowires using the transmission line method (TLM) on a cylindrical geometry. InAs nanowire resistors are fabricated on Si substrates using a hydrogen silsesquioxane (HSQ) spacer between the bottom and top contact. The thickness of the HSQ is defined by the dose of an electron beam lithography step, and by varying the separation thickness for a group of resistors, a TLM series is fabricated. Using this method, the resistivity and specific contact resistance are determined for InAs nanowires with different doping and annealing conditions. The contacts are shown to improve with annealing at temperatures up to 300 degrees C for 1min, with specific contact resistance values reaching down to below 1 Omega mu m(2). (C) 2015 AIP Publishing LLC.
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| 4. |
- Berg, Martin, et al.
(författare)
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Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si
- 2016
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Ingår i: IEEE Electron Device Letters. - 0741-3106. ; 37:8, s. 966-969
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Tidskriftsartikel (refereegranskat)abstract
- Vertical InAs nanowire transistors are fabricated on Si using a gate-last method, allowing for lithography-based control of the vertical gate length. The best devices combine good ON- and OFF-performance, exhibiting an ON-current of 0.14 mA/μm, and a sub-threshold swing of 90 mV/dec at 190 nm LG. The device with the highest transconductance shows a peak value of 1.6 mS/μm. From RF measurements, the border trap densities are calculated and compared between devices fabricated using the gate-last and gate-first approaches, demonstrating no significant difference in trap densities. The results thus confirm the usefulness of implementing digital etching in thinning down the channel dimensions.
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| 5. |
- Berg, Martin, et al.
(författare)
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Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si
- 2016
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Ingår i: Technical Digest - International Electron Devices Meeting, IEDM. - 9781467398930 ; 2016-February
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Konferensbidrag (refereegranskat)abstract
- In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.
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| 6. |
- Hellenbrand, Markus, et al.
(författare)
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Capacitance Measurements in Vertical III-V Nanowire TFETs
- 2018
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Ingår i: IEEE Electron Device Letters. - 0741-3106. ; 39:7, s. 943-946
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Tidskriftsartikel (refereegranskat)abstract
- By measuring scattering parameters over a wide range of bias points, we study the intrinsic gate capacitance as well as the charge partitioning of vertical nanowire tunnel field-effect transistors (TFETs). The gate-to-drain capacitance Cgd is found to largely dominate the on-state of TFETs, whereas the gate-to-source capacitance Cgs is sufficiently small to be completely dominated by parasitic components. This indicates that the tunnel junction on the source side almost completely decouples the channel charge from the small-signal variation in the source, while the absence of a tunnel junction on the drain side allows the channel charge to follow the drain small-signal variation much more directly.
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| 7. |
- Hellenbrand, Markus, et al.
(författare)
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Comparison of Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
- 2019
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- We compare III-V nanowire (NW) metal-oxidesemiconductor field-effect transistors (MOSFETs) in a vertical gate-all-around (GAA) as well as a lateral trigate architecture with planar reference MOSFETs and reveal that the NW geometry does not deteriorate the low-frequency noise (LFN) performance. In fact, with gate oxides deposited at the same conditions, the NW structures show potential to achieve better metrics due to slightly lower border trap densities Nbt. The normalized LFN in transistors with a higher number of NW can degrade due to averaging effects between individual nanowires within the same device.
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| 8. |
- Hellenbrand, Markus, et al.
(författare)
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Effect of Gate Oxide Defects on Tunnel Transistor RF Performance
- 2018
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Ingår i: 2018 76th Device Research Conference (DRC). - 9781538630280 ; , s. 137-138
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Tunnel field-effect transistors (TFETs) are designed for low off-state leakage and low drive voltages. To investigate how capable TFETs are of RF operation, we measured their scattering parameters and performed small-signal modeling. We find that in the low frequency ranges, gate oxide defects have a major influence on the RF performance of these devices, which can be modeled by a frequency-dependent gate-to-drain conductance ggd;w. This model is based on charge trapping in gate oxide defects and was studied before for metal-oxide-semiconductor capacitors.
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| 9. |
- Hellenbrand, Markus, et al.
(författare)
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Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
- 2019
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317.
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Tidskriftsartikel (refereegranskat)abstract
- Nanowire geometries are leading contenders for future low-power transistor design. In this study, low-frequency noise is measured and evaluated in highly scaled III-V nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs) and in planar III-V MOSFETs to investigate to what extent the device geometry affects the noise performance. Number fluctuations are identified as the dominant noise mechanism in both architectures. In order to perform a thorough comparison of the two architectures, a discussion of the underlying noise model is included. We find that the noise performance of the MOSFETs in a nanowire architecture is at least comparable to the planar devices. The input-referred voltage noise in the nanowire devices is superior by at least a factor of four.
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| 10. |
- Hellenbrand, Markus, et al.
(författare)
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Random telegraph signal noise in tunneling field-effect transistors with S below 60 mV/decade
- 2017
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Ingår i: 47th European Solid-State Device Research Conference (ESSDERC), 2017. - 9781509059799 - 9781509059782 ; , s. 38-41
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Single gate oxide defects in strongly scaled Tunneling Field-Effect Transistors with an inverse subthreshold slope well below 60 mV/decade are investigated by Random Telegraph Signal (RTS) noise measurements. The cause for RTS noise are electrons being captured in and released from individual defects in the gate oxide. Under the assumption that elastic tunneling is the underlying capture and emission mechanism, the measured RTS time constants vary with the relative position of the channel Fermi level and the defect energy level while the amplitudes — independent of the capture and release mechanism — follow the inverse of the inverse subthreshold slope.
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