| 1. |
- Strand, Robin, 1978-, et al.
(författare)
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Holistic whole-body MRI image analysis
- 2016
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Ingår i: Symposium of the Swedish Society for Automated Image Analysis, Uppsala, Sweden, (SSBA).
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)
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| 2. |
- Loutfi, Amy, 1978-, et al.
(författare)
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Ecare@home : A distributed research environment on semantic interoperability
- 2016
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Ingår i: Lect. Notes Inst. Comput. Sci. Soc. Informatics Telecommun. Eng.. - Cham : Springer International Publishing. - 9783319512334 - 9783319512341 ; , s. 3-8
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Konferensbidrag (refereegranskat)abstract
- This paper presents the motivation and challenges to developing semantic interoperability for an internet of things network that is used in the context of home based care. The paper describes a research environment which examines these challenges and illustrates the motivation through a scenario whereby a network of devices in the home is used to provide high-level information about elderly patients by leveraging from techniques in context awareness, automated reasoning, and configuration planning.
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| 3. |
- Zota, Cezar B., et al.
(författare)
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InGaAs nanowire MOSFETs with ION = 555 μa/μm at IOFF = 100 nA/μm and VDD = 0.5 v
- 2016
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Ingår i: 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. - 9781509006373
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Konferensbidrag (refereegranskat)abstract
- We report on In0.85Ga0.15As nanowire MOSFETs (NWFETs) with record performance in several key VLSI metrics. These devices exhibit ION = 555 μA/μm (at IOFF = 100 nA/μm and VDD = 0.5 V), ION = 365 μA/μm (at IOFF = 10 nA/μm and VDD = 0.5 V) and a quality factor Q = gm/SS of 40, all of which are the highest reported for a III-V as well as silicon transistor. Furthermore, a highly scalable, self-Aligned gate-last fabrication process is utilized, with a single nanowire as the channel. The devices use a 45° angle between the nanowire and the contacts, which allows for up to a 1.4 times longer gate length at a given pitch.
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| 4. |
- Berg, Martin, et al.
(författare)
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Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si
- 2016
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Ingår i: IEEE Electron Device Letters. - 0741-3106. ; 37:8, s. 966-969
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Tidskriftsartikel (refereegranskat)abstract
- Vertical InAs nanowire transistors are fabricated on Si using a gate-last method, allowing for lithography-based control of the vertical gate length. The best devices combine good ON- and OFF-performance, exhibiting an ON-current of 0.14 mA/μm, and a sub-threshold swing of 90 mV/dec at 190 nm LG. The device with the highest transconductance shows a peak value of 1.6 mS/μm. From RF measurements, the border trap densities are calculated and compared between devices fabricated using the gate-last and gate-first approaches, demonstrating no significant difference in trap densities. The results thus confirm the usefulness of implementing digital etching in thinning down the channel dimensions.
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| 5. |
- Berg, Martin, et al.
(författare)
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Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si
- 2016
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Ingår i: Technical Digest - International Electron Devices Meeting, IEDM. - 9781467398930 ; 2016-February
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Konferensbidrag (refereegranskat)abstract
- In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.
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| 6. |
- Jansson, Kristofer, et al.
(författare)
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Amplifier Design Using Vertical InAs Nanowire MOSFETs
- 2016
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383. ; 63:6, s. 2353-2359
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, an amplifier design using ballistic vertical InAs nanowire (NW) transistors is investigated, focusing on a basic common-source amplifier. The maximum power gain at 90 GHz is evaluated for different NW transistor architectures together with the power dissipation. The linearity of the amplifier is evaluated by estimating the IIP3 and 1-dB compression points. Furthermore, the impact of the parasitic capacitances and resistances is quantified and it is demonstrated that the gain may be increased by a cascode design. It is concluded that a power gain exceeding 20 dB at 90 GHz may be achieved by a common-source amplifier based on an InAs NW transistor architecture. A power consumption below 1 mW is possible, while still maintaining a high power gain. Furthermore, IIP3 exceeding 10 dBm is predicted. The combination of these qualities makes the NW transistor architecture an attractive prospect for low-power amplifiers at millimeter wave frequencies.
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| 7. |
- Memisevic, Elvedin, et al.
(författare)
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Scaling of Vertical InAs–GaSb Nanowire Tunneling Field-Effect Transistors on Si
- 2016
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Ingår i: IEEE Electron Device Letters. - 0741-3106. ; 37:5, s. 549-552
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Tidskriftsartikel (refereegranskat)abstract
- We demonstrate improved performance due to enhanced electrostatic control achieved by diameter scaling and gate placement in vertical InAs-GaSb tunneling field-effect transistors integrated on Si substrates. The best subthreshold swing, 68 mV/decade at VDS=0.3 V, was achieved for a device with 20-nm InAs diamter. The on-current for the same device was 35 µA/µm at VGS=0.5 V and VDS=0.5 V. The fabrication technique used allows downscaling of the InAs diameter down to 11 nm with a flexible gate placement.
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| 8. |
- Roll, Guntrade, et al.
(författare)
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Effect of Gate Voltage Stress on InGaAs MOSFET with HfO2 or Al2O3 Dielectric
- 2016
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Ingår i: IEEE Transactions on Device and Materials Reliability. - 1530-4388. ; 16:2, s. 112-116
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Tidskriftsartikel (refereegranskat)abstract
- InGaAs nMOSFETs with Al2O3 and HfO2 as dielectric are analyzed. The devices with Al 2O3 show a slightly better subthreshold slope. Both high-κ's have an equal transconductance frequency dispersion (gm-f). A reduction of gm-f is reached by scaling the HfO2 thickness. Positive gate stress leads to an increase in threshold voltage and subthreshold slope for all oxides. DC-gmax degradation is related purely to creation or activation of additional border traps during stress. The RF-gmax is not degraded. Similar time constants hint to a relation between the (semi-)stable degradation of DC-gmax and the threshold voltage increase. For the samples with HfO2, the effects of gate-stress induced additional border traps can only be detected at low frequencies. The created or activated defects are most likely located deep in the oxide. For Al2O3, the effect of additional border traps is also measurable at higher frequencies. The defects are created both closer to the Al2O3/InGaAs interface and deeper in the oxide.
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| 9. |
- Shiri Babadi, Aein, et al.
(författare)
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ZrO2 and HfO2 dielectrics on (001) n-InAs with atomic-layer-deposited in situ surface treatment
- 2016
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Ingår i: Applied Physics Letters. - : AIP Publishing. - 0003-6951 .- 1077-3118. ; 108:13
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Tidskriftsartikel (refereegranskat)abstract
- The electrical properties of ZrO2 and HfO2 gate dielectrics on n-InAs were evaluated. Particularly, an in situ surface treatment method including cyclic nitrogen plasma and trimethylaluminum pulses was used to improve the quality of the high-κ oxides. The quality of the InAs-oxide interface was evaluated with a full equivalent circuit model developed for narrow band gap metal-oxide-semiconductor (MOS) capacitors. Capacitance-voltage (C-V) measurements exhibit a total trap density profile with a minimum of 1 × 1012 cm-2 eV-1 and 4 × 1012 cm-2 eV-1 for ZrO2 and HfO2, respectively, both of which are comparable to the best values reported for high-κ/III-V devices. Our simulations showed that the measured capacitance is to a large extent affected by the border trap response suggesting a very low density of interface traps. Charge trapping in MOS structures was also investigated using the hysteresis in the C-V measurements. The experimental results demonstrated that the magnitude of the hysteresis increases with increase in accumulation voltage, indicating an increase in the charge trapping response.
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| 10. |
- Wu, Jun, et al.
(författare)
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RF Characterization of Vertical Wrap-Gated InAs/High-κ Nanowire Capacitors
- 2016
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383. ; 63:2, s. 584-589
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents RF as well as low-frequency capacitance–voltage (C–V) characterization of vertical wrap-gated InAs/high-κ nanowire MOS capacitors. A full equivalent circuit model for traps is used to fit the low-frequency C–V characteristics, from which the interface trap density (Dit) and border trap density (Nbt) are evaluated separately. The results show comparable Nbt but far lower Dit (<10E12 eV−1cm−2 near the conduction band edge) for a nanowire MOS gate-stack compared with planar references. In the RF domain, the influence of nanowire series resistances become significant, and by introducing a distributed RC-model, the nanowire resistivity (ρnw) is evaluated from the capacitance data as a function of the gate bias. An ON/OFF ρnw ratio of 10E−2 is obtained for the best device. Using the measured data, the quality factor is finally evaluated both for fabricated and ideal capacitors. The results agree well with simulated data.
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