| 1. |
- Hellenbrand, Markus, et al.
(författare)
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Comparison of Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
- 2019
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- We compare III-V nanowire (NW) metal-oxidesemiconductor field-effect transistors (MOSFETs) in a vertical gate-all-around (GAA) as well as a lateral trigate architecture with planar reference MOSFETs and reveal that the NW geometry does not deteriorate the low-frequency noise (LFN) performance. In fact, with gate oxides deposited at the same conditions, the NW structures show potential to achieve better metrics due to slightly lower border trap densities Nbt. The normalized LFN in transistors with a higher number of NW can degrade due to averaging effects between individual nanowires within the same device.
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| 2. |
- Krishnaraja, Abinaya, et al.
(författare)
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Fabrication of Tunnel FETs demonstrating sub-thermal subthreshold slope
- 2019
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Konferensbidrag (refereegranskat)abstract
- Tunnel Field Effect Transistor (TFET), based on band-to-band tunneling, overcomes the thermal limit (subthreshold slope (S) > 60 mV/decade) of the MOSFETs by filtering the high-energy Fermi tail, thereby allowing a substantial reduction of supply voltage and power consumption. Despite the steep slope behavior, TFETs can suffer from ambipolarity wherein carriers tunnel into the channel at both high positive and negative gate voltages. In this work, we demonstrate the fabrication of InAs/InGaAsSb/GaSb vertical nanowire TFET devices and present experimental data showcasing suppressed ambipolarity and a minimum S = 39 mV/decade at Vds=0.05V. The nanowires were grown using MOVPE where the 100nm long InAs drain was n-doped with TESn followed by a 100nm undoped InAs channel and a 100nm/300nm DEZn doped InGaAsSb/GaSb source. After growth, the InAs was selectively digitally etched using citric acid to reduce the channel diameter from 40nm to 25nm. The electrostatics was improved, compared to our previously reported devices, with a gate stack of ALD bilayer of 1nm/3nm Al2O3/HfO2 (EOT~1nm) followed by 30nm sputtered W. To decrease the ambipolar conduction, a gate-drain underlap of approximately 20nm was used which widens the tunnel barrier at the drain junction. Since the gate length is defined by the bottom spacer thickness in vertical transistors, the underlap provides a shorter gate positioned close to the source-channel junction. Thus the new process scheme has improved the slope and reduced the OFF current by one order of magnitude compared to our previous devices [1]. [1] E. Memisevic et al., IEEE Trans.ElectronDevices,vol.64,4746–4751, 2017.
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| 3. |
- Lind, Carl Mikael, et al.
(författare)
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Prevention of Work: Related Musculoskeletal Disorders Using Smart Workwear – The Smart Workwear Consortium
- 2019
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Ingår i: Human Systems Engineering and Design. - Cham : Springer. - 9783030020521 - 9783030020538 ; 876, s. 477-483
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Konferensbidrag (refereegranskat)abstract
- Adverse work-related physical exposures such as repetitive movements and awkward postures have negative health effects and lead to large financial costs. To address these problems, a multi-disciplinary consortium was formed with the aim of developing an ambulatory system for recording and analyzing risks for musculoskeletal disorders utilizing textile integrated sensors as part of the regular workwear. This paper presents the consortium, the Smart Workwear System, and a case study illustrating its potential to decrease adverse biomechanical exposure by promoting improved work technique.
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