| 1. |
- Hemani, Ahmed, et al.
(författare)
-
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
- 1999
-
Ingår i: Design Automation Conference, 1999. Proceedings. 36th. ; , s. 873-878
-
Konferensbidrag (refereegranskat)abstract
- Power consumption in clock of large high performance VLSIs can be reduced by adopting globally asynchronous, locally synchronous design style (GALS). GALS has small overheads for the global asynchronous communication and local clock generation. We propose methods to (a) evaluate the benefits of GALS and account for its overheads, which can be used as the basis for partitioning the system into optimal number/size of synchronous blocks, and (b) automate the synthesis of the global asynchronous communication. Three realistic ASICs, ranging in complexity from 1 to 3 million gates, were used to evaluate GALS benefits and overheads. The results show an average power saving of about 70% in clock with negligible overheads
|
|
| 2. |
- Hemani, Ahmed, et al.
(författare)
-
Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style
- 1999
-
Ingår i: Proceedings of the 36th ACM/IEEE conference on Design automation. - New York, NY, USA : ACM. ; , s. 873-878
-
Konferensbidrag (refereegranskat)abstract
- Power consumption in clock of large high performance VLSIs can be reduced by adopting Globally Asynchronous, Locally Synchronous design style (GALS). GALS has small overheads for the global asynchronous communication and local clock generation. We propose methods to a) evaluate the benefits of GALS and account for its overheads, which can be used as the basis for partitioning the system into optimal number/size of synchronous blocks, and b) automate the synthesis of the global asynchronous communication. Three realistic ASICs, ranging in complexity from 1 to 3 million gates, were used to evaluate GALS benefits and overheads. The results show an average power saving of about 70% in clock with negligible overheads.
|
|
| 3. |
- Meincke, Thomas, et al.
(författare)
-
Globally asynchronous locally synchronous architecture for large high-performance ASICs
- 1999
-
Ingår i: ; 2, s. 512-515
-
Konferensbidrag (refereegranskat)abstract
- Clock nets are the major source of power consumption in large, high-performance ASICs and a design bottleneck when it comes to tolerable clock skew. A way to obviate the global clock net is to partition the design into large synchronous blocks each having its own clock. Data with other blocks is exchanged asynchronously using handshake signals. Adopting such a strategy requires a methodology that supports: 1) a partitioning method dividing a design into the number of synchronous blocks such that the gain due to global clock net removal exceeds the communication overhead and 2) synthesis of handshake protocols to implement the data transfer between synchronous blocks. We describe this methodology and present results of applying it to a realistic design done in 0.25 micron, ranging in operating frequencies from 20 MHz to 1 GHz. The results show that the net power savings compared to fully synchronous designs are on an average about 30%
|
|
| 4. |
|
|
| 5. |
- Olsson, Thomas, et al.
(författare)
-
A Digitally Controlled Low-Power Clock Multiplier for Globally Asynchronous Locally Synchronous Designs
- 2000
-
Ingår i: The 2000 IEEE International Symposium on Circuits and Systems. Proceedings.. - 0780354826 ; 3, s. 13-16
-
Konferensbidrag (refereegranskat)abstract
- Partitioning large high-speed globally synchronous ASICs into locally clocked blocks reduces clock skew problems and if handled correctly it also reduces the power consumption. However, to achieve these positive effects, the blocks need on-chip clock generators having properties such as small area and low power consumption. Therefore, a low power, high frequency, small area digitally controlled on-chip clock generator is designed and fabricated using a 0.35 μm process. The clock generator delivers up to 1.15 GHz at 3.3 V supply voltage. At 1 V supply voltage, it delivers up to 92 MHz while consuming 0.16 mW
|
|
| 6. |
- Olsson, Thomas, et al.
(författare)
-
A digitally controlled on-chip clock multiplier for globally asynchronous locally synchronous systems
- 1999
-
Ingår i: Circuits and Systems, 1999. 42nd Midwest Symposium on. ; 1, s. 84-87
-
Konferensbidrag (refereegranskat)abstract
- For large high-speed globally synchronous ASICs, designing the clock distribution net becomes a troublesome task. Besides problems caused by clock skew, the clock net also is a major source of power consumption. Partitioning the design into locally clocked blocks reduces clock skew problems and if handled correctly it also helps reducing power consumption. However, to achieve these positive effects, the blocks need on-chip clocks having properties as small area and low power consumption. Therefore, a low power small area digitally controlled on-chip clock generator is designed
|
|
| 7. |
- Olsson, Thomas, et al.
(författare)
-
A digitally controlled PLL for digital SOCs
- 2003
-
Ingår i: Proceedings - IEEE International Symposium on Circuits and Systems. - 2158-1525 .- 0271-4310. ; 5, s. 437-440
-
Konferensbidrag (refereegranskat)abstract
- A fully integrated digitally controlled PLL used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. It is therefore portable between processes as an IP-block. Using a 0.35 μm standard CMOS process and a 3.0 V supply, the PLL has a frequency range of 152 MHz to 366 MHz and occupies an on-chip area of about 0.07 mm2. In addition, the next version of this all-digital PLL is described in synthesizable VHDL-code, which simplifies digital system simulation and change of process. A new time-to-digital converter with simulated resolution of 250 ps is made for the next PLL.
|
|
| 8. |
- Olsson, Thomas, et al.
(författare)
-
A digitally controlled PLL for SoC applications
- 2004
-
Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200. ; 39:5, s. 751-760
-
Tidskriftsartikel (refereegranskat)abstract
- A fully integrated digitally controlled phase-locked loop (PLL) used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. The design is, therefore, portable between technologies as an IP block. Using a 0.35-mum standard CMOS process and a 3.0-V supply voltage, the PLL has a frequency range of 152 to 366 MHz and occupies an on-chip area of 0.07 mm(2). In addition, the next version of this all-digital PLL is described in synthesizable VHDL code, which simplifies digital system simulation and change of process. A new time-to-digital converter with higher resolution is designed for the improved PLL. An improved digitally controlled oscillator is also suggested.
|
|
| 9. |
- Olsson, Thomas, et al.
(författare)
-
A fully Integrated Standard-Cell Digital PLL
- 2001
-
Ingår i: Electronics Letters. - : Institution of Engineering and Technology (IET). - 1350-911X .- 0013-5194. ; 37:4, s. 211-212
-
Tidskriftsartikel (refereegranskat)abstract
- A fully integrated digital phase-locked loop (PLL) used as a clock multiplying circuit is designed. The PLL is made from standard cells found in almost any commercial standard cell library and therefore portable between processes in netlist format. Using a 0.35 μm standard complementary metal-oxide-semiconductor CMOS process and a 3.0 V supply voltage, the PLL is designed for a locking range of 170 to 360 MHz and occupies an on-chip area of 0.06 mm2
|
|
| 10. |
- Olsson, Thomas, et al.
(författare)
-
A low-complexity method for distributed clocking on digital ASICs
- 2004
-
Ingår i: Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (IEEE Cat. No.04EX909). - 078038637X ; , s. 344-347
-
Konferensbidrag (refereegranskat)abstract
- A low-complexity method using synchronous wrappers is proposed to simplify communication between modules using unsynchronized clocks. To test the method, it is implemented together with a divider and an FFT co-processor. The divider with synchronous wrapper and local clock generator, delivering a 500 MHz clock, is synthesized and verified using post-synthesis simulations for a 0.18 μm 1.8 V CMOS technology. A complete description of the wrapper in synthesizable VHDL-code including local a local clock generator makes the method portable between technologies
|
|
