| 1. |
- Ahmad, Naeem
(författare)
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Modelling and optimization of sky surveillance visual sensor network
- 2012
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- A Visual Sensor Network (VSN) is a distributed system of a largenumber of camera sensor nodes. The main components of a camera sensornode are image sensor, embedded processor, wireless transceiver and energysupply. The major difference between a VSN and an ordinary sensor networkis that a VSN generates two dimensional data in the form of an image, whichcan be exploited in many useful applications. Some of the potentialapplication examples of VSNs include environment monitoring, surveillance,structural monitoring, traffic monitoring, and industrial automation.However, the VSNs also raise new challenges. They generate large amount ofdata which require higher processing powers, large bandwidth requirementsand more energy resources but the main constraint is that the VSN nodes arelimited in these resources.This research focuses on the development of a VSN model to track thelarge birds such as Golden Eagle in the sky. The model explores a number ofcamera sensors along with optics such as lens of suitable focal length whichensures a minimum required resolution of a bird, flying at the highestaltitude. The combination of a camera sensor and a lens formulate amonitoring node. The camera node model is used to optimize the placementof the nodes for full coverage of a given area above a required lower altitude.The model also presents the solution to minimize the cost (number of sensornodes) to fully cover a given area between the two required extremes, higherand lower altitudes, in terms of camera sensor, lens focal length, camera nodeplacement and actual number of nodes for sky surveillance.The area covered by a VSN can be increased by increasing the highermonitoring altitude and/or decreasing the lower monitoring altitude.However, it also increases the cost of the VSN. The desirable objective is toincrease the covered area but decrease the cost. This objective is achieved byusing optimization techniques to design a heterogeneous VSN. The core ideais to divide a given monitoring range of altitudes into a number of sub-rangesof altitudes. The sub-ranges of monitoring altitudes are covered by individualsub VSNs, the VSN1 covers the lower sub-range of altitudes, the VSN2 coversthe next higher sub-range of altitudes and so on, such that a minimum cost isused to monitor a given area.To verify the concepts, developed to design the VSN model, and theoptimization techniques to decrease the VSN cost, the measurements areperformed with actual cameras and optics. The laptop machines are used withthe camera nodes as data storage and analysis platforms. The area coverage ismeasured at the desired lower altitude limits of homogeneous as well asheterogeneous VSNs and verified for 100% coverage. Similarly, the minimumresolution is measured at the desired higher altitude limits of homogeneous aswell as heterogeneous VSNs to ensure that the models are able to track thebird at these highest altitudes.
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| 2. |
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| 3. |
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| 4. |
- Imran, Muhammad
(författare)
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Investigation of Architectures for Wireless Visual Sensor Nodes
- 2011
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Wireless visual sensor network is an emerging field which has proveduseful in many applications, including industrial control and monitoring,surveillance, environmental monitoring, personal care and the virtual world.Traditional imaging systems used a wired link, centralized network, highprocessing capabilities, unlimited storage and power source. In manyapplications, the wired solution results in high installation and maintenancecosts. However, a wireless solution is the preferred choice as it offers lessmaintenance, infrastructure costs and greater scalability.The technological developments in image sensors, wirelesscommunication and processing platforms have paved the way for smartcamera networks usually referred to as Wireless Visual Sensor Networks(WVSNs). WVSNs consist of a number of Visual Sensor Nodes (VSNs)deployed over a large geographical area. The smart cameras can performcomplex vision tasks using limited resources such as batteries or alternativeenergy sources, embedded platforms, a wireless link and a small memory.Current research in WVSNs is focused on reducing the energyconsumption of the node so as to maximise the life of the VSN. To meet thischallenge, different software and hardware solutions are presented in theliterature for the implementation of VSNs.The focus in this thesis is on the exploration of energy efficientreconfigurable architectures for VSNs by partitioning vision tasks on software,hardware platforms and locality. For any application, some of the vision taskscan be performed on the sensor node after which data is sent over the wirelesslink to the server where the remaining vision tasks are performed. Similarly,at the VSN, vision tasks can be partitioned on software and the hardwareplatforms.In the thesis, all possible strategies are explored, by partitioning visiontasks on the sensor node and on the server. The energy consumption of thesensor node is evaluated for different strategies on software platform. It isobserved that performing some of the vision tasks on the sensor node andsending compressed images to the server where the remaining vision tasks areperformed, will have lower energy consumption.In order to achieve better performance and low power consumption,Field Programmable Gate Arrays (FPGAs) are introduced for theimplementation of the sensor node. The strategies with reasonable designtimes and costs are implemented on hardware-software platform. Based onthe implementation of the VSN on the FPGA together with micro-controller,the lifetime of the VSN is predicted using the measured energy values of theplatforms for different processing strategies. The implementation resultsprove our analysis that a VSN with such characteristics will result in a longerlife time.
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| 5. |
- Khursheed, Khursheed
(författare)
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Investigation of intelligence partitioning in wireless visual sensor networks
- 2011
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The wireless visual sensor network is an emerging field which is formed by deploying many visual sensor nodes in the field and in which each individual visual sensor node contains an image sensor, on board processor, memory and wireless transceiver. In comparison to the traditional wireless sensor networks, which operate on one dimensional data, the wireless visual sensor networks operate on two dimensional data which requires higher processing power and communication bandwidth. Research focus within the field of wireless visual sensor networks has been on two different extremes, involving either sending raw data to the central base station without local processing or conducting all processing locally at the visual sensor node and transmitting only the final results.This research work focuses on determining an optimal point of hardware/software partitioning at the visual sensor node as well as partitioning tasks between local and central processing, based on the minimum energy consumption for the vision processing tasks. Different possibilities in relation to partitioning the vision processing tasks between hardware, software and locality for the implementation of the visual sensor node, used in wireless visual sensor networks have been explored. The effect of packets relaying and node density on the energy consumption and implementation of the individual wireless visual sensor node, when used in a multi-hop wireless visual sensor networks have also been explored.The lifetime of the visual sensor node is predicted by evaluating the energy requirement of the embedded platform with a combination of the Field Programmable Gate Arrays (FPGA) and the micro-controller for the implementation of the visual sensor node and, in addition, taking into account the amount of energy required for receiving/forwarding the packets of other nodes in the multi-hop network.Advancements in FPGAs have been the motivation behind their choice as the vision processing platform for implementing visual sensor node. This choice is based on the reduced time-to-market, low Non-Recurring Engineering (NRE) cost and programmability as compared to ASICs. The other part of the architecture of the visual sensor node is the SENTIO32 platform, which is used for vision processing in the software implementation of the visual sensor node and for communicating the results to the central base station in the hardware implementation (using the RF transceiver embedded in SENTIO32).
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| 6. |
- Lawal, Najeem, 1974-
(författare)
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Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
- 2006
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include object recognition, object tracking and surveillance. Developments in field programmable gate array (FPGA) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operation are currently available optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis. A method for the optimal use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) codes for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimal use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components. The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components.
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| 8. |
- Lidholm, Jörgen
(författare)
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Stereo vision algorithms in reconfigurable hardware for robotics applications
- 2011
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- This thesis presents image processing solutions in FPGA based embedded vision systems. Image processing is a demanding process but the information that can be extracted from images is very useful and can be used for many tasks like mapping and navigation, object detection and recognition, collision detection and more. Image processing or analysis involves reading images from a camera system, improve an image with respect to colour fidelity and white balance, removing distortion, extracting salient information. The mentioned steps are often referred to as low to medium level image processing and involve large amounts of data and fairly simple algorithms suitable for parallel processing. Medium to high level processing involves a reduced amount of data and more complex algorithms. Object recognition which involves matching image features to information stored in a database is of higher complexity. A vision system can be used in anything from a car to industry processes to mobile robots playing soccer or assisting people in their homes. A vision system often works with video streams that are processed to find pieces that can be handled in an industry process, detect obstacles that may be potential hazards in traffic or to find and track landmarks in the environment that can be used to build and navigate from. This involves large amount of calculations and this is a problem, even though modern computers are fast they may still not be able to execute the desired algorithms with the frequency wanted. Even if there are computers that are fast enough they are bulky and require a lot of power. They are not suitable for incorporating on small mobile robots. In this thesis I will present the image processing sequence to give an understanding of the complexity of the processes involved and I will discuss some processing platforms suitable for image processing. I will also present my work that is focused on image algorithm implementations for reconfigurable hardware suitable for mobile robots with requirements on speed an power consumption.
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| 9. |
- Lundgren, Jan, 1977-
(författare)
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Behavioral Level Simulation Methods for Early Noise Coupling Quantification in Mixed-Signal Systems
- 2005
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- In this thesis, noise coupling simulation is introduced into the behavioral level. Methods and models for simulating on-chip noise coupling at a behavioral level in a design flow are presented and verified for accuracy and validity. Today, designs of electronic systems are becoming denser and more and more mixed-signal systems such as System-on-Chip (SoC) are being devised. This raises problems when the electronics components start to interfere with each other. Often, digital components disturb analog components, introducing noise into the system causing degradation of the performance or even introducing errors into the functionality of the system. Today, these effects can only be simulated at a very late stage in the design process, causing large design iterations and increased costs if the designers are required to return and make alterations, which may have occurred at a very early stage in the process. This is why the focus of this work is centered on extracting noise coupling simulation models that can be used at a very early design stage such as the behavioral level and then follow the design through the various design stages. To realize this, SystemC is selected as a platform and implementation example for the behavioral level models. SystemC supports design refinement, which means that when designs are being refined and are crossing the design levels, the noise coupling models can also be refined to suit the current design. This new way of thinking in primarily mixed-signal designs is called Behavioral level Noise Coupling (BeNoC) simulation and shows great promise in enabling a reduction in the costs of design iterations due to component cross-talk and simplifies the work for mixed-signal system designers.
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| 10. |
- Meng, Xiaozhou
(författare)
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Maintenance Consideration for Long Life Cycle Embedded System
- 2012
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- In this thesis, the work presented is in relation to consideration to the maintenance of a long life cycle embedded system. Various issues can present problems for maintaining a long life cycle embedded system, such as component obsolescence and IP (intellectual property) portability. For products including automotive, avionics, military application etc., the desired life cycles for these systems are many times longer than the obsolescence cycle for the electronic components used in the systems. The maintainability is analyzed in relation to long life cycle embedded systems for different design technologies. FPGA platform solutions are proposed in order to ease the system maintenance. Different platform cases are evaluated by analyzing the essence of each case and the consequences of different risk scenarios during system maintenance. This has shown that an FPGA platform with a vendor and device independent soft IP has the highest maintainability.A mathematic model of obsolescence management for long life cycle embedded system maintenance is presented. This model can estimate the minimum management costs for the different system architecture and this consists of two parts. The first is to generate a graph in Matlab which is in the form of state transfer diagram. A segments table is then output from Matlab for further optimization. The second part is to find the lowest cost in the state transfer diagram, which can be viewed as a transshipment problem. Linear programming is used to calculate the minimized management cost and schedule, which is solved by Lingo. A simple Controller Area Network (CAN) controller system case study is shown in order to apply this model. The model is validated by a set of synthetic and experimentally selected values. The results provided by this are a minimized management cost and an optimized management time schedule. Test experiments of the maintenance cost responding to the interest rate and unit cost are implemented. The responses from the experiments meet our expectations. The reuse of predefined IP can shorten development times and assist the designer to meet time-to-market (TTM) requirements. System migration between devices is unavoidable, especially when it has a long life cycle expectation, so IP portability becomes an important issue for system maintenance. An M-JPEG decoder case study is presented in the thesis. The lack of any clear separation between computation and communication is shown to limit the IP’s portability with respect to different communication interfaces. A methodology is proposed to ease the interface modification and interface reuse, thus to increase the portability of an IP. Technology and tool dependent firmware IP components are also shown to limit the IP portability with respect to development tools and FPGA vendors.
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