| 1. |
- Jönsson, Adam, et al.
(author)
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Doping Profiles in Ultrathin Vertical VLS-Grown InAs Nanowire MOSFETs with High Performance
- 2021
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In: ACS Applied Electronic Materials. - : American Chemical Society (ACS). - 2637-6113. ; 3:12, s. 5240-5247
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Journal article (peer-reviewed)abstract
- Thin vertical nanowires based on III-V compound semiconductors are viable candidates as channel material in metal oxide semiconductor field effect transistors (MOSFETs) due to attractive carrier transport properties. However, for improved performance in terms of current density as well as contact resistance, adequate characterization techniques for resolving doping distribution within thin vertical nanowires are required. We present a novel method of axially probing the doping profile by systematically changing the gate position, at a constant gate length Lg of 50 nm and a channel diameter of 12 nm, along a vertical nanowire MOSFET and utilizing the variations in threshold voltage VT shift (∼100 mV). The method is further validated using the well-established technique of electron holography to verify the presence of the doping profile. Combined, device and material characterizations allow us to in-depth study the origin of the threshold voltage variability typically present for metal organic chemical vapor deposition (MOCVD)-grown III-V nanowire devices.
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| 2. |
- Jönsson, Adam, et al.
(author)
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Gate-Length Dependence of Vertical GaSb Nanowire p-MOSFETs on Si
- 2020
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In: IEEE Transactions on Electron Devices. - 0018-9383. ; 67:10, s. 4118-4122
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Journal article (peer-reviewed)abstract
- The effect of gate-length variation on key transistor metrics for vertical nanowire p-type GaSb metal-oxide-semiconductor field-effect transistors (MOSFETs) are demonstrated using a gate-last process. The new fabrication method enables short gate-lengths (Lg = 40 nm) and allows for selective digital etching of the channel region. Extraction of material properties as well as contact resistance are obtained by systematically varying the gate-length. The fabricated transistors show excellent modulation properties with a maximum Ion/Ioff = 700 (VGS = -0.5,,V) as well as peak transconductance of 50 μS/μm with a linear subthreshold swing of 224 mV/dec.
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| 3. |
- Kilpi, Olli Pekka, et al.
(author)
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High-Performance Vertical III-V Nanowire MOSFETs on Si with gm> 3 mS/μm
- 2020
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In: IEEE Electron Device Letters. - 0741-3106. ; 41:8, s. 1161-1164
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Journal article (peer-reviewed)abstract
- Vertical III-V nanowire MOSFETs have demonstrated excellent performance including high transconductance and high Ion. One main bottleneck for the vertical MOSFETs is the large access resistance arising from the contacts and ungated regions. We demonstrate a process to reduce the access resistance by combining a gate-last process with ALD gate-metal deposition. The devices demonstrate fully scalable gm down to Lg = 25 nm. These vertical core/shell InAs/InGaAs MOSFETs demonstrate gm = 3.1 mS/μm and Ron = 190 Ωμm. This is the highest gm demonstrated on Si. Transmission line measurement verifies a low contact resistance with RC = 115 Ωμm, demonstrating that most of the MOSFET access resistance is located in the contact regions.
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| 4. |
- Kilpi, Olli Pekka, et al.
(author)
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Increased Breakdown Voltage in Vertical Heterostructure III-V Nanowire MOSFETs with a Field Plate
- 2021
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In: IEEE Electron Device Letters. - 0741-3106. ; 42:11, s. 1596-1598
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Journal article (peer-reviewed)abstract
- Vertical III-V heterostructure MOSFETs exhibit outstanding performance at reduced supply voltages. In this paper, we report on a novel process of extending high-speed device operation towards higher voltages. The device vertical geometry allows for engineering a field plate by covering the nanowire drain area with a 10-nm-thick SiO2 film. The film acts as a field moderator in the device drain region. Reference devices without a field plate exhibit a transconductance of 2.5 mS/μm, while devices with a 120-nm-long field plate show 1.5 mS/μm but a three times increase in breakdown voltage. Measurements show that the field-screening effect attributes to reduced band-to-band tunneling and impact ionization, thereby reducing the parasitic bipolar effect in the MOSFET channel as well. The devices show promise in applications in circuits and systems requiring large power-handling.
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| 5. |
- Kilpi, Olli-Pekka, et al.
(author)
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Vertical nanowire III–V MOSFETs with improved high-frequency gain
- 2020
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In: Electronics Letters. - : Institution of Engineering and Technology (IET). - 1350-911X .- 0013-5194. ; 56:13, s. 669-671
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Journal article (peer-reviewed)abstract
- High-frequency performance of vertical InAs/InGaAs heterostructure nanowire MOSFETs on Si is demonstrated for the first time for a gate-last configuration. The device architecture allows highly asymmetric capacitances, which increases the power gain. A device with Lg = 120 nm demonstrates fT = 120 GHz, fmax = 130 GHz and maximum stable gain (MSG) = 14.4 dB at 20 GHz. These metrics demonstrate the state-of-the-art performance of vertical nanowire MOSFETs.
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| 6. |
- Krishnaraja, Abinaya, et al.
(author)
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Tuning of Source Material for InAs/InGaAsSb/GaSb Application-Specific Vertical Nanowire Tunnel FETs
- 2020
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In: ACS Applied Electronic Materials. - : American Chemical Society (ACS). - 2637-6113. ; 2:9, s. 2882-2887
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Journal article (peer-reviewed)abstract
- Tunnel field-effect transistors (TFETs) are promising candidates that have demonstrated potential for and beyond the 3 nm technology node. One major challenge for the TFETs is to optimize the heterojunction for high drive currents while achieving steep switching. Thus far, such optimization has mainly been addressed theoretically. Here, we experimentally investigate the influence of the source segment composition on the performance for vertical nanowire InAs/InGaAsSb/GaSb TFETs. Compositional analysis using transmission electron microscopy is combined with simulations to interpret the results from electrical characterization data. The results show that subthreshold swing (S) and transconductance (gm) decrease with increasing arsenic composition until the strain due to lattice mismatch increases them both. The role of indium concentration at the junction is also examined. This systematic optimization has rendered sub-40 mV/dec operating TFETs with a record transconductance efficiency gm/ID = 100 V-1, and it shows that different source materials are preferred for various applications.
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| 7. |
- Dzhigaev, Dmitry, et al.
(author)
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Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction
- 2020
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In: Nanoscale. - : Royal Society of Chemistry (RSC). - 2040-3372 .- 2040-3364. ; 12:27, s. 14487-14493
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Journal article (peer-reviewed)abstract
- Semiconductor nanowires in wrapped, gate-all-around transistor geometry are highly favorable for future electronics. The advanced nanodevice processing results in strain due to the deposited dielectric and metal layers surrounding the nanowires, significantly affecting their performance. Therefore, non-destructive nanoscale characterization of complete devices is of utmost importance due to the small feature sizes and three-dimensional buried structure. Direct strain mapping inside heterostructured GaSb-InAs nanowire tunnel field-effect transistor embedded in dielectric HfO2, W metal gate layers, and an organic spacer is performed using fast scanning X-ray nanodiffraction. The effect of 10 nm W gate on a single embedded nanowire with segment diameters down to 40 nm is retrieved. The tensile strain values reach 0.26% in the p-type GaSb segment of the transistor. Supported by the finite element method simulation, we establish a connection between the Ar pressure used during the W layer deposition and the nanowire strain state. Thus, we can benchmark our models for further improvements in device engineering. Our study indicates, how the significant increase in X-ray brightness at 4th generation synchrotron, makes high-throughput measurements on realistic nanoelectronic devices viable.
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| 8. |
- Krishnaraja, Abinaya, et al.
(author)
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Vertical InAs/InGaAsSb/GaSb Nanowire Tunnel FETs on Si with Drain Field-Plate and EOT = 1 nm Achieving Smin= 32 mV/dec and gm/ID= 100 V-1
- 2020
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In: 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020. - 9781728197357 ; , s. 17-18
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Conference paper (peer-reviewed)abstract
- We present vertical InAs/InGaAsSb/GaSb nanowire tunnel FETs (TFETs) on Si demonstrating subthreshold swing (S) of 32 mV/dec with ION = 4 µA/µm for IOFF = 1 nA/µm at VDS = 0.3V. The demonstrated drive currents is the highest reported for a TFET with S below 40 mV/dec resulting in a transconductance efficiency as high as 100 V-1. These results have been achieved by optimizing the source segment growth scheme and the device processing. The devices are compliant with low-power logic applications capable of operation at IOFF = 100 pA/µm.
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| 9. |
- Löfstrand, Anette, et al.
(author)
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Feature size control using surface reconstruction temperature in block copolymer lithography for InAs nanowire growth
- 2020
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In: Nanotechnology. - : IOP Publishing. - 0957-4484 .- 1361-6528. ; 31:32
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Journal article (peer-reviewed)abstract
- Here we present a method to control the size of the openings in hexagonally organized BCP thin films of poly(styrene)-block-poly(4-vinylpyridine) (PS-b-P4VP) by using surface reconstruction. The surface reconstruction is based on selective swelling of the P4VP block in ethanol, and its extraction to the surface of the film, resulting in pores upon drying. We found that the BCP pore diameter increases with ethanol immersion temperature. In our case, the temperature range 18 to 60 °C allowed fine-Tuning of the pore size between 14 and 22 nm. A conclusion is that even though the molecular weight of the respective polymer blocks is fixed, the PS-b-P4VP pore diameter can be tuned by controlling temperature during surface reconstruction. These results can be used for BCP-based nanofabrication in general, and for vertical nanowire growth in particular, where high pattern density and diameter control are of importance. Finally, we demonstrate successful growth of indium arsenide InAs vertical nanowires by selective-Area metal-organic vapor phase epitaxy (MOVPE), using a silicon nitride mask patterned by the proposed PS-b-P4VP surface reconstruction lithography method.
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| 10. |
- Persson, Anton E. O., et al.
(author)
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A method for estimating defects in ferroelectric thin film MOSCAPs
- 2020
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In: Applied Physics Letters. - : AIP Publishing. - 0003-6951 .- 1077-3118. ; 117:24
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Journal article (peer-reviewed)abstract
- We propose a capacitance measurement scheme that enables quantitative characterization of ferroelectric thin films integrated onsemiconductors. The film defect density is estimated by measurements of the CV hysteresis and frequency dispersion, whereas importantdevice parameters such as memory window and endurance can be extracted by a unidirectional CV method. The simple measurementscheme and the usage of metal-oxide-semiconductor capacitors rather than MOSFETs make the proposed methods suitable for the futureoptimization of ferroelectric field effect transistor and negative capacitance field effect transistor gate stacks. Specifically, we present data forthe narrow bandgap semiconductor InAs and show that low temperature characterization is critical to reduce the influence of the minoritycarrier response; however, the methods should be transferrable to room temperature for semiconductors with a wider bandgap. Our resultsclearly indicate that the defect density of the HfxZr1xO2 (HZO) films increases at the crystallization temperature, but the increase is modestand remains independent of the annealing temperature at even more elevated temperatures. It is also shown that the shrinkage of thememory window caused by field cycling is not accompanied by an increase in defect density.
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