| 1. |
- Wang, Guilei, et al.
(författare)
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Growth of SiGe layers in source and drain regions for 10 nm node complementary metal-oxide semiconductor (CMOS)
- 2020
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Ingår i: Journal of materials science. Materials in electronics. - : Springer Science and Business Media LLC. - 0957-4522 .- 1573-482X. ; 31, s. 26-33
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Tidskriftsartikel (refereegranskat)abstract
- In this study, the integration of Si 1−x Ge x (50% ≤ x ≤ 60%) selective epitaxy on source/drain regions in 10 nm node FinFET has been presented. One of the major process issues was the sensitivity of Si-fins’ shape to ex- and in-situ cleaning prior to epitaxy. For example, the sharpness of Si-fins could easily be damaged during the wafer washing. The results showed that a DHF dip before the normal cleaning, was essential to clean the Si-fins while in-situ annealing in range of 780–800 °C was needed to remove the native oxide for high epitaxial quality. Because of smallness of fins, the induced strain by SiGe could not be directly measured by X-ray beam in a typical XRD tool in the lab or even in a Synchrotron facility. Further analysis using nano-beam diffraction technique in high-resolution transmission electron microscope also failed to provide information about strain in the FinFET structure. Therefore, the induced strain by SiGe was simulated by technology computer-aided design program and the Ge content was measured by using energy dispersive spectroscopy. Simulation results showed 0.8, 1 and 1.3 GPa for Ge content of 40%, 50% and 60%, respectively. A kinetic gas model was also introduced to predict the SiGe profile on Si-fins with sharp triangular shape. The input parameters in the model includes growth temperature, partial pressure of the reactant gases and the exposed Si coverage in the chip area.
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| 2. |
- Gu, Limin, et al.
(författare)
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Case Studies on the Use of Technology in TPD (Teacher Professional Development)
- 2012
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Ingår i: US-China Education Review. A. - : David Publishing Company. - 2161-623X .- 1548-6613 .- 1930-1529. ; 2:3, s. 278-290
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, the progress of a three-year cooperative project investigating the current state of TPD (teacher professional development) in Sweden and China in the area of TPD and ICT (information and communication technologies) is summarized. A brief introduction to the field of TPD is given, and thereafter, ICT is related to what in the project is referred to as TETPD (Technology Enhanced Teacher Professional Development). Thereafter, the project as such is given a short presentation, followed by findings regarding policies and initiatives related to TETPD in Sweden and China for investigating the current state of TETPD in each country respectively. The framework for investigating TETPD is presented, and four Chinese and four Swedish cases are compared to some facets showing differences in models for TETPD in the two countries.
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| 3. |
- Kehoe, Laura, et al.
(författare)
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Make EU trade with Brazil sustainable
- 2019
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Ingår i: Science. - : American Association for the Advancement of Science (AAAS). - 0036-8075 .- 1095-9203. ; 364:6438, s. 341-
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Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)
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| 4. |
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| 5. |
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| 6. |
- Qin, C., et al.
(författare)
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A novel method for source/drain ion implantation for 20 nm FinFETs and beyond
- 2020
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Ingår i: Journal of materials science. Materials in electronics. - : Springer Science and Business Media LLC. - 0957-4522 .- 1573-482X. ; 31, s. 98-104
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a method to improve source/drain extension (SDE) ion implantation (I/I) process for sub-20 nm node FinFETs with no extra step in transistor process. Traditionally, SDE I/I process needs a large implant tilt angle and a high dose to obtain a heavy and conformal doping. However, this process leads to implantation shadow effects and Si-fin amorphization. These drawbacks can be removed in our new approach when SDE I/I is modified and moved after S/D epitaxy process (SDE I/I-last). Because of the facet planes of the SiGe layer, the ions are allowed to be implanted with small tilt. This is helpful to avoid shadow effects of implantation and to keep the low defect density in the S/D. As a result, the external resistance (R EXTRNL ) is not high and the strain relaxation is minor in S/D epitaxy layer. Finally, p-type FinFETs with 25 nm gate length with SDE I/I-last are fabricated. These new FinFETs demonstrate ~ 50% on-state current (I ON ) improvement compared to those transistors fabricated by traditional method.
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