| 1. |
- Chen, Zhe, et al.
(författare)
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Toward FPGA Security in IoT : A New Detection Technique for Hardware Trojans
- 2019
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Ingår i: IEEE Internet of Things Journal. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 2327-4662. ; 6:4, s. 7061-7068
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Tidskriftsartikel (refereegranskat)abstract
- Nowadays, field programmable gate array (FPGA) has been widely used in Internet of Things (IoT) since it can provide flexible and scalable solutions to various IoT requirements. Meanwhile, hardware Trojan (HT), which may lead to undesired chip function or leak sensitive information, has become a great challenge for FPGA security. Therefore, distinguishing the Trojan-infected FPGAs is quite crucial for reinforcing the security of IoT. To achieve this goal, we propose a clock-tree-concerned technique to detect the HTs on FPGA. First, we present an experimental framework which helps us to collect the electromagnetic (EM) radiation emitted by FPGA clock tree. Then, we propose a Trojan identifying approach which extracts the mathematical feature of obtained EM traces, i.e., 2-D principal component analysis (2DPCA) in this paper, and automatically isolates the Trojan-infected FPGAs from the Trojan-free ones by using a BP neural network. Finally, we perform extensive experiments to evaluate the effectiveness of our method. The results reveal that our approach is valid in detecting HTs on FPGA. Specifically, for the trust-hub benchmarks, we can find out the FPGA with always on Trojans (100% detection rate) while identifying the triggered Trojans with high probability (by up to 92%). In addition, we give a thorough discussion on how the experimental setup, such as probe step size, scanning area, and chip ambient temperature, affects the Trojan detection rate.
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| 2. |
- Guo, Shize, et al.
(författare)
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Securing IoT Space via Hardware Trojan Detection
- 2020
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Ingår i: IEEE Internet of Things Journal. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 2327-4662. ; 7:11, s. 11115-11122
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Tidskriftsartikel (refereegranskat)abstract
- Hardware Trojan (HT) is a malicious modification in the chip circuitry, which may lead to undesired chip function changing or sensitive information leaking once activated. As recently studied, HT has become one of the main threats for Internet-of-Things (IoT) security, and therefore, protecting IoT against the HT attack attracts growing attention from IoT researchers. In this article, we propose an HT detection technique which makes use of chip temporal thermal information and self-organizing map (SOM) neural network to automatically isolate the Trojan-infected chips with the Trojan-free ones, and meanwhile, confirm the Trojan location at the infected chips. The experimental results reveal that our method is effective. Specifically, for the Trust-hub benchmarks, it can detect HTs which increase only 0.02% power consumption of the original design and localize the Trojan positions precisely without any error. In addition, we demonstrate the advantages of our method over two existing HT detection methods, namely, the thermal and power map (TPM) and ring oscillator net (RON), and make a thorough discussion on how the thermal image resolution, chip technology, and clustering algorithm affect the Trojan detection results.
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| 3. |
- Wang, Jian, et al.
(författare)
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A New Parallel CODEC Technique for CDMA NoCs
- 2018
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Ingår i: IEEE Transactions on Industrial Electronics. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 0278-0046 .- 1557-9948. ; 65:8, s. 6527-6537
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Tidskriftsartikel (refereegranskat)abstract
- Code division multiple access (CDMA) network-on-chip (NoC) has been proposed for many-core systems due to its data transfer parallelism over communication channels. Consequently, coder-decoder (CODEC) module, which greatly impacts the performance of CDMA NoCs, attracted growing attention in recent years. In this paper, we propose a new parallel CODEC technique for CDMA NoCs. In general, by using a few simple logic circuits with small penalties in area and power, our new parallel (NPC) CODEC can execute the encoding/decoding process in parallel and thus reduce the data transfer latency. To reveal the benefits of our method for on-chip communication, we apply our NPC to CDMA NoCs and perform extensive experiments. From the results, we can find that our method outperforms existing parallel CODECs, such as Walsh-based parallel CODEC (WPC) and overloaded parallel CODEC (OPC). Specifically, it improves the critical point of communication latency (7.3% over WPC and 13.5% over OPC), reduces packet latency jitter by about 17.3% (against WPC) and 71.6% (against OPC), and improves energy efficiency by up to 41.2% (against WPC) and 59.2% (against OPC).
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| 4. |
- Wang, Jian, et al.
(författare)
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ACO-Based Thermal-Aware Thread-to-Core Mapping for Dark-Silicon-Constrained CMPs
- 2017
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Ingår i: IEEE Transactions on Electron Devices. - : IEEE Press. - 0018-9383 .- 1557-9646. ; 64:3, s. 930-937
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Tidskriftsartikel (refereegranskat)abstract
- The limitation on thermal budget in chip multiprocessor (CMP) results in a fraction of inactive silicon regions called dark silicon, which significantly impacts the system performance. In this paper, we propose a thread-to-core mapping method for dark-silicon-constrainedCMPs to address their thermal issue. We first propose a thermal predictionmodel to forecast CMP temperature after the CMP executes a forthcoming application. Then, we develop an ant colony optimization-based algorithm to conduct the thread-to- core mapping process, such that the CMP peak temperature is minimized and, consequently, the probability of triggering CMP dynamic thermal management is decreased. Finally, we evaluate our method and compare it with the baseline (a standard Linux scheduler) and other existing methods (NoC-Sprinting, DaSiM mapping, and TP mapping). The simulation results show that our method gains good thermal profile and computational performance, and performs well with chip scaling. Specifically, it eliminates all thermal emergency time, outperforming all other methods, and gains million instructions per second improvement up to 12.9% against the baseline.
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