| 1. |
- Chen, X. Y., et al.
(författare)
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Application of weak ferromagnetic BiFeO3 films as the photoelectrode material under visible-light irradiation
- 2007
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Ingår i: Applied Physics Letters. - : American Institute of Physics (AIP). - 0003-6951 .- 1077-3118. ; 91:2, s. 022114-
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Tidskriftsartikel (refereegranskat)abstract
- BiFeO3 films prepared by pulsed laser deposition on Pt/TiO2/SiO2/Si substrates were studied as photoelectrode for water splitting. Under visible-light irradiation, the photocurrent intensity of the polycrystalline BiFeO3 film was found to double that of the amorphous one in a three-electrode cell. The incident photon to current conversion efficiency for the polycrystalline BiFeO3 electrode was approximately 16% at 350 nm and 7% at 530 nm at 1.5 V (versus saturated calomel electrode). The ferromagnetism of the amorphous BiFeO3 film was an order of magnitude weaker than that of the polycrystalline one, supporting the "size effect" explanation for magnetic origin. (C) 2007 American Institute of Physics.
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| 2. |
- Queralta, J. P., et al.
(författare)
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FPGA-based Architecture for a Low-Cost 3D Lidar Design and Implementation from Multiple Rotating 2D Lidars with ROS
- 2019
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Ingår i: Proceedings of IEEE Sensors. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781728116341
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Konferensbidrag (refereegranskat)abstract
- Three-dimensional representations and maps are the key behind self-driving vehicles and many types of advanced autonomous robots. Localization and mapping algorithms can achieve much higher levels of accuracy with dense 3D point clouds. However, the cost of a multiple-channel three-dimensional lidar with a 360°field of view is at least ten times the cost of an equivalent single-channel two-dimensional lidar. Therefore, while 3D lidars have become an essential component of self-driving vehicles, their cost has limited their integration and penetration within smaller robots. We present an FPGA-based 3D lidar built with multiple inexpensive RPLidar A1 2D lidars, which are rotated via a servo motor and their signals combined with an FPGA board. A C++ package for the Robot Operating System (ROS) has been written, which publishes a 3D point cloud. The mapping of points from the two-dimensional lidar output to the three-dimensional point cloud is done at the FPGA level, as well as continuous calibration of the motor speed and lidar orientation based on a built-in landmark recognition. This inexpensive design opens a wider range of possibilities for lower-end and smaller autonomous robots, which can be able to produce three-dimensional world representations. We demonstrate the possibilities of our design by mapping different environments.
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| 3. |
- Nguyen Gia, T., et al.
(författare)
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Edge AI in Smart Farming IoT : CNNs at the Edge and Fog Computing with LoRa
- 2019
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Ingår i: IEEE AFRICON Conference. - : Institute of Electrical and Electronics Engineers (IEEE).
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Konferensbidrag (refereegranskat)abstract
- The agricultural and farming industries have been widely influenced by the disruption of the Internet of Things. The impact of the IoT is more limited in countries with less penetration of mobile internet such as sub-Saharan countries, where agriculture commonly accounts for 10 to 50% of their GPD. The boom of low-power wide-area networks (LPWAN) in the last decade, with technologies such as LoRa or NB-IoT, has mitigated this providing a relatively cheap infrastructure that enables low-power and long-range transmissions. Nonetheless, the benefits that LPWAN technologies enable have the disadvantage of low-bandwidth transmissions. Therefore, the integration of Edge and Fog computing, moving data analytics and compression near end devices, is key in order to extend functionality. By integrating artificial intelligence at the local network layer, or Edge AI, we present a system architecture and implementation that expands the possibilities of smart agriculture and farming applications with Edge and Fog computing and LPWAN technology for large area coverage. We propose and implement a system consisting on a sensor node, an Edge gateway, LoRa repeaters, Fog gateway, cloud servers and end-user terminal application. At the Edge layer, we propose the implementation of a CNN-based image compression method in order to send in a single message information about hundreds or thousands of sensor nodes within the gateway's range. We use advanced compression techniques to reduce the size of data up to 67% with a decompression error below 5%, within a novel scheme for IoT data.
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| 4. |
- Chu, H., et al.
(författare)
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An ASIC Design of Multi-Electrode Digital Basket Catheter Systems with Reconfigurable Compressed Sampling
- 2019
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Ingår i: International System on Chip Conference. - : IEEE Computer Society. - 9781538614907 ; , s. 308-313
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Konferensbidrag (refereegranskat)abstract
- This paper presents an Application Specific Integrated Circuit (ASIC) design with reconfigurable compressed sampling (CS) for multi-electrode basket catheter systems that acquire intracardiac electrograms (IEGMs). This work adopts a reconfigurable CS (ReCS) encoder for near-electrode processing to enable sub-Nyquist sampling rate thus improve the system capacity. The ReCS encoder is designed to work with a reconfigurable compression cycle as well as a reconfigurable compression ratio, which makes it suitable for a wide range of different signals. This digital ASIC chip is placed at the distal end of the catheter close to electrodes, so that all signals have been digitalized and encoded before transmitting to an external receiver. Such architecture ensures serial data transmission, reducing number of traces and size of the catheter, as well as fabrication complexity. Evaluated area cost of total digital circuits is 0.046 mm 2 and the power consumption is 49.1 μW with 4 MHz clock frequency in 65 nm process.
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| 5. |
- Qingqing, L., et al.
(författare)
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Detecting Water Reflection Symmetries in Point Clouds for Camera Position Calibration in Unmanned Surface Vehicles
- 2019
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Ingår i: Proceedings. - : Institute of Electrical and Electronics Engineers Inc.. ; , s. 507-512
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Konferensbidrag (refereegranskat)abstract
- The development of autonomous vehicles has seen considerable advances over the past decade. However, specific challenges remain in the area of autonomous waterborne navigation. Two key aspects in autonomous surface vehicles are sensor calibration and segmentation of water surface. Cameras and other sensors in a car or drone can be installed accurately in a specific position and orientation. In a large vessel, this is not always possible, as sensors might be installed around the vessel or on masts. Taking advantage of the medium in which these vehicles operate, the water plane can be used as a reference for different sensors to calibrate their orientation. This allows more accurate localization of obstacles of objects. State-of-the-art deep learning techniques have been successfully applied for water surface segmentation in open sea. However, in other environments such as small rivers or lakes with still waters, a different approach might enable more accurate water surface estimation. We propose a method to estimate the water plane based on the detection of local symmetry planes that naturally occur when objects are reflected in the water. By using a point cloud generated with a stereo camera, we are able to accurately estimate the water level and, at the same time, calibrate the camera position and improve the localization of obstacles. We assume that an approximate position and orientation of the camera is known with respect to the sea level. We demonstrate the efficiency of our method with data obtained in the Aura river, Finland, with our prototype vessel facing both the riverside and the center of the river.
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| 6. |
- Qingqing, L., et al.
(författare)
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Edge Computing for Mobile Robots : Multi-Robot Feature-Based Lidar Odometry with FPGAs
- 2019
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Ingår i: 2019 12th International Conference on Mobile Computing and Ubiquitous Network, ICMU 2019. - : Institute of Electrical and Electronics Engineers (IEEE).
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Konferensbidrag (refereegranskat)abstract
- Offloading computationally intensive tasks such as lidar or visual odometry from mobile robots has multiple benefits. Resource constrained robots can make use of their network capabilities to reduce the data processing load and be able to perform a larger number tasks in a more efficient manner. However, previous works have mostly focused on cloud offloading, which increases latency and reduces reliability, or high-end edge devices. Instead, we explore the utilization of FPGAs at the edge for computational offloading with minimal latency and high parallelism. We present the potential for modelling feature-based odometry in VHDL and utilizing FPGA implementations.
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| 7. |
- Xu, J., et al.
(författare)
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A Low-Power Arithmetic Element for Multi-Base Logarithmic Computation on Deep Neural Networks
- 2019
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Ingår i: International System on Chip Conference. - : IEEE Computer Society. - 9781538614907 ; , s. 260-265
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Konferensbidrag (refereegranskat)abstract
- Computational complexity and memory intensity are crucial in deep convolutional neural network algorithms for deployment to embedded systems. Recent advances in logarithmic quantization has manifested great potential in reducing the inference cost of neural network models. However, current base-2 logarithmic quantization suffers from performance upper limit and there is few work that studies hardware implementation of other bases. This paper presents a multi-base logarithmic scheme for Deep Neural Networks (DNNs). The performance of Alexnet is studied with respects to different quantization resolutions. Base -\sqrt2 logarithmic quantization is able to raise the ceiling of top-5 classifying accuracy from 69.3% to 75.5% at 5-bit resolution. A segmented logarithmic quantization method that combines both base-2 and base \sqrt2 is then proposed to improve the network top-5 accuracy to 72.3% in 4-bit resolution. The corresponding arithmetic element hardware has been designed, which supports base sqrt2 logarithmic quantization and segmented logarithmic quantization respectively. Evaluated in UMC 65nm process, the proposed arithmetic element operating at 500MHz and 1.2V consumes as low as 120 μW. Compared with 16-bit fixed point multiplier, our design achieves 58.03% smaller in area, with 73.74% energy reduction.
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| 8. |
- Xu, J., et al.
(författare)
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A Memory-Efficient CNN Accelerator Using Segmented Logarithmic Quantization and Multi-Cluster Architecture
- 2021
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 68:6, s. 2142-2146
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a memory-efficient CNN accelerator design for resource-constrained devices in Internet of Things (IoT) and autonomous systems. A segmented logarithmic (SegLog) quantization method is exploited to mitigate the on-chip memory and bandwidth requirements, thus accommodating more processing elements (PEs) in a given chip area to organize a reconfigurable multi-cluster architecture. Such algorithm-architecture joint optimization improves the utilization and efficiency of memory resources. SegLog quantization adopting mixed bases optimizes fixed-points placement in different segmentations and improves network accuracy at low-precision representation, while the multi-cluster architecture can reorganize PEs to adapt to various CNN models for efficient dataflow and multi-level data reuse. The evaluation results show that SegLog quantization can achieve 6.4× model compression with 1.73%, 0.74%, 2.11%, and 1.76% accuracy penalty on AlexNet, VGG16, ResNet34, and DenseNet161, respectively. An ASIC implementation with 168 PEs configuration is validated in a 40-nm CMOS process, with 2.54 TOPs/W energy efficiency and 0.8 mm chip area reported. The accelerator has also been implemented on FPGA with 1512 PEs configured and 468 kB on-chip memory thanks to the extensibility of the architecture. It delivers up to 604.8 GOPs performance at 200 MHz, corresponding to a 1.29 GOPs/kB memory efficiency. Compared with the state-of-the-art accelerators, our ASIC implementation enhances area efficiency and arithmetic intensity by 1.94× and 5.62×, while the FPGA implementation achieves the memory efficiency improvement by a factor of 2.34×. IEEE
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