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  • Collin, Mikael, et al. (författare)
  • A performance and energy exploration of dictionary code compression architectures
  • 2011
  • Ingår i: 2011 International  Green Computing Conference and Workshops (IGCC). - IEEE conference proceedings. - 978-1-4577-1222-7 ; s. 1-8
  • Konferensbidrag (refereegranskat)abstract
    • We have made a performance and energy exploration of a previously proposed dictionary code compression mechanism where frequently executed individual instructions and/or sequences are replaced in memory with short code words. Our simulated design shows a dramatically reduced instruction memory access frequency leading to a performance improvement for small instruction cache sizes and to significantly reduced energy consumption in the instruction fetch path. We have evaluated the performance and energy implications of three architectural parameters: branch prediction accuracy, instruction cache size and organization. To asses the complexity of the design we have implemented the critical stages in VHDL.
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  • Deb, Abhijit Kumar, et al. (författare)
  • Hardware software codesign of DSP system using grammar based approach
  • 2001
  • Ingår i: VLSI Design, 2001. Fourteenth International Conference on. ; s. 42-47
  • Konferensbidrag (refereegranskat)abstract
    • Embedded cores are gaining widespread use to deal with the complex DSP systems where flexibility is of utmost importance. The design of such a system offers several problems, which are not addressed by the existing methodology. The authors previously presented an integrated grammar based DSP design methodology that separates architectural and functional specification, can create a virtual prototype and has a smooth link to the implementation phase. In this paper we present the extension of the work to handle embedded cores. Here we the capture the host peripheral interface (HPI) of TMS320C6x core at higher level of abstraction and provide a single simulation environment, which facilitates faster analysis of hardware software components. Our results reveal that the proposed methodology offers simulation time speed-up of 5 times and design time speed-up of 8 times, while keeping the architectural specification separated from functionality
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