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Träfflista för sökning "WFRF:(Johansson Lars Erik) ;pers:(Egard Mikael);srt2:(2010)"

Sökning: WFRF:(Johansson Lars Erik) > Egard Mikael > (2010)

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  • Egard, Mikael, et al. (författare)
  • Vertical InAs nanowire wrap gate transistors with f(t) > 7 GHz and f(max) > 20 GHz.
  • 2010
  • Ingår i: Nano Letters. - The American Chemical Society. - 1530-6992. ; 10:3, s. 809-812
  • Tidskriftsartikel (refereegranskat)abstract
    • In this letter we report on high-frequency measurements on vertically standing III-V nanowire wrap-gate MOSFETs (metal-oxide-semiconductor field-effect transistors). The nanowire transistors are fabricated from InAs nanowires that are epitaxially grown on a semi-insulating InP substrate. All three terminals of the MOSFETs are defined by wrap around contacts. This makes it possible to perform high-frequency measurements on the vertical InAs MOSFETs. We present S-parameter measurements performed on a matrix consisting of 70 InAs nanowire MOSFETs, which have a gate length of about 100 nm. The highest unity current gain cutoff frequency, f(t), extracted from these measurements is 7.4 GHz and the maximum frequency of oscillation, f(max), is higher than 20 GHz. This demonstrates that this is a viable technique for fabricating high-frequency integrated circuits consisting of vertical nanowires.
  • Lind, Erik, et al. (författare)
  • High Frequency Performance of Vertical InAs Nanowire MOSFET
  • 2010
  • Ingår i: 2010 22Nd International Conference On Indium Phosphide And Related Materials (Iprm). - IEEE--Institute of Electrical and Electronics Engineers Inc.. - 1092-8669. - 978-1-4244-5919-3
  • Konferensbidrag (refereegranskat)abstract
    • We report on RF characterization of vertical, 100-nm-gate length InAs nanowire MOSFETs, utilizing wrap-gate technology and Al2O3 high-kappa gate oxide. The transistors show f(t)=5.6 GHz and f(max)=22 GHz, mainly limited by parasitic capacitances. The RF device performance is described using a hybrid-pi model taking hole generation at the drain into account. Electrostatic modeling of the parasitic capacitances for arrays of vertical nanowires indicates that a strong reduction in extrinsic capacitances can be achieved for devices with a small inter-wire separation.
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