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Träfflista för sökning "WFRF:(Nilsson Peter) ;pers:(Torkelson Mats)"

Sökning: WFRF:(Nilsson Peter) > Torkelson Mats

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  • Nilsson, Peter, et al. (författare)
  • A bit-serial CMOS digital IF-filter for mobile radio using an on-chip clock
  • 1994
  • Ingår i: Mobile communications advanced systems and components / Lecture notes in Computer Science. - Springer-Verlag. - 0302-9743. - 3-540-57856-0 ; 783, s. 510-521
  • Konferensbidrag (refereegranskat)abstract
    • A chip for digital intermediate frequency filtering is introduced. The filter is intended move most of the analog intermediate frequency filtering to the digital domain in systems like the American mobile radio system (IS-54). It is a wave digital lattice filter realized with bit-serial arithmetic. Furthermore, a technique for local clocks on chip is presented. The method is based on a ring oscillator and a cycle counter which is controlled from outside the chip. A 0.8 micron technology custom test chip has been fabricated and tested.
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  • Nilsson, Peter, et al. (författare)
  • A bit-serial realization of a lattice wave digital intermediate frequency filter
  • 1993
  • Ingår i: Proc. Sixth Annual IEEE Int. ASIC Conf. and Exhibit, ASIC'93. - 0-7803-1375-5 ; s. 197-200
  • Konferensbidrag (refereegranskat)abstract
    • A custom DSP chip for mobile radio systems like the American IS-54 system is presented. The application is a digital intermediate frequency filter which is intended to replace expensive analog filters. It is a lattice wave digital filter with fixed coefficient bit-serial arithmetic. A technique which is useful for area efficient layouts in high throughput real time signal processing is discussed.
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  • Nilsson, Peter, et al. (författare)
  • A Custom Digital Intermediate Frequency Filter for the American Mobile Telephone System
  • 1997
  • Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200. ; 32:6, s. 806-815
  • Tidskriftsartikel (refereegranskat)abstract
    • A digital filter for intermediate frequency filtering in mobile communication systems is presented. The purpose of the work is to show an alternative to the analog filters which are used in most of today's heterodyne receivers. Bit-serial arithmetic is applied on a twelfth-order wave digital lattice filter algorithm. The paper also shows a method for retiming such algorithms. The power consumption in two fabricated prototypes is compared. By customizing the library cells, the power consumption has been reduced significantly. In the low power prototype, the power dissipation is 8 mW using 3 V supply voltage. The prototype is a 10 MIPS design fabricated in a 0.8-μm standard two-metal-layer CMOS process
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  • Nilsson, Peter, et al. (författare)
  • A Monolithic Digital Clock-Generator for On-Chip Clocking of Custom DSP's
  • 1996
  • Ingår i: IEEE Journal of Solid-State Circuits. - IEEE. - 0018-9200. ; 31:5, s. 700-706
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper shows a robust and easily implemented clock generator for custom designs. It is a fully digital design suitable for both high-speed clocking and low-voltage applications. This clocking method is digital, and it avoids analog methods like phase locked loops or delay line loops. Instead, the clock generator is based on a ring counter which stops a ring oscillator after the correct number of cycles. Both a 385 MHz clock and a 15 MHz custom DSP application using the on-chip clocking strategy are described. The prototypes have been fabricated in a 0.8 μm standard CMOS process. The major advantages with this clocking method are robustness, small size, low-power consumption, and that it can operate at a very low supply voltage
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  • Resultat 1-10 av 28
  • [1]23Nästa
 
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