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Träfflista för sökning "WFRF:(Soudris Dimitrios) "

Sökning: WFRF:(Soudris Dimitrios)

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  • Candaele, Bernard, et al. (författare)
  • Mapping Optimisation for Scalable multi-core ARchiTecture : The MOSART approach
  • 2010
  • Ingår i: Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010. - 978-076954076-4 ; s. 518-523
  • Konferensbidrag (refereegranskat)abstract
    • The project will address two main challenges of prevailing architectures: 1) The global Interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures Including middleware services and a run-time data manager for NoC based communication infrastructure; 2) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.
  • Candaele, Bernard, et al. (författare)
  • The MOSART Mapping Optimization for multi-core Architectures
  • 2011
  • Ingår i: VLSI 2010 Annual Symposium. - Springer Publishing Company. ; s. 181-195
  • Konferensbidrag (refereegranskat)abstract
    • MOSART project addresses two main challenges of prevailing architectures: (i) Theglobal interconnect and memory bottleneck due to a single, globally shared memorywith high access times and power consumption; (ii) The difficulties in programmingheterogeneous, multi-core platforms MOSART aims to overcome these through amulti-core architecture with distributed memory organization, a Network-on-Chip(NoC) communication backbone and configurable processing cores that are scaled,optimized and customized together to achieve diverse energy, performance, cost andsize requirements of different classes of applications. MOSART achieves this by:(i) Providing platform support for management of abstract data structures includingmiddleware services and a run-time data manager for NoC based communicationinfrastructure; (ii) Developing tool support for parallelizing and mapping applicationson the multi-core target platform and customizing the processing cores for theapplication.
  • Smaragdos, Georgios, et al. (författare)
  • BrainFrame: a node-level heterogeneous accelerator platform for neuron simulations
  • 2017
  • Ingår i: JOURNAL OF NEURAL ENGINEERING. - 1741-2560. ; 14:6
  • Tidskriftsartikel (refereegranskat)abstract
    • Objective: The advent of High-Performance Computing (HPC) in recent years has led to its increasing use in brain study through computational models. The scale and complexity of such models are constantly increasing, leading to challenging computational requirements. Even though modern HPC platforms can often deal with such challenges, the vast diversity of the modeling field does not permit for a homogeneous acceleration platform to effectively address the complete array of modeling requirements. Approach: In this paper we propose and build BrainFrame, a heterogeneous acceleration platform that incorporates three distinct acceleration technologies, an Intel Xeon-Phi CPU, a NVidia GP-GPU and a Maxeler Dataflow Engine. The PyNN software framework is also integrated into the platform. As a challenging proof of concept, we analyze the performance of BrainFrame on different experiment instances of a state-of-the-art neuron model, representing the Inferior-Olivary Nucleus using a biophysically-meaningful, extended Hodgkin-Huxley representation. The model instances take into account not only the neuronal-network dimensions but also different network-connectivity densities, which can drastically affect the workload's performance characteristics. Main results: The combined use of different HPC fabrics demonstrated that BrainFrame is better able to cope with the modeling diversity encountered in realistic experiments. Our performance analysis shows clearly that the model directly affects performance and all three technologies are required to cope with all the model use cases. Significance: The BrainFrame framework is designed to transparently configure and select the appropriate back-end accelerator technology for use per simulation run. The PyNN integration provides a familiar bridge to the vast number of models already available. Additionally, it gives a clear roadmap for extending the platform support beyond the proof of concept, with improved usability and directly useful features to the computational-neuroscience community, paving the way for wider adoption.
  • Soudris, Dimitrios, et al. (författare)
  • AEGLE : A Big Bio-Data Analytics Framework for Integrated Health-Care Services
  • 2015
  • Ingår i: Proceedings International Conference on Embedded Computer Systems - Architectures, Modeling and Simulation (SAMOS XV). - 9781467373111 ; s. 246-253
  • Konferensbidrag (refereegranskat)abstract
    • AEGLE project(1) targets to build an innovative ICT solution addressing the whole data value chain for health based on: cloud computing enabling dynamic resource allocation, HPC infrastructures for computational acceleration and advanced visualization techniques. In this paper, we provide an analysis of the addressed Big Data health scenarios and we describe the key enabling technologies, as well as data privacy and regulatory issues to be integrated into AEGLE's ecosystem, enabling advanced health-care analytic services, while also promoting related research activities.
  • Anagnostopoulos, Iraklis, et al. (författare)
  • Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations
  • 2011
  • Ingår i: IEEE Embedded Systems Letters. - 1943-0663. ; 3:2, s. 66-69
  • Tidskriftsartikel (refereegranskat)abstract
    • Multiprocessor system-on-chip (MPSoCs) have attracted significant attention since they are recognized as a scalable paradigm to interconnect and organize a high number of cores. Current multicore embedded systems exhibit increased levels of dynamicbehavior, leading to unexpected memory footprint variations unknown at design time.Dynamic memory management (DMM) is a promising solution for such types of dynamicsystems. Although some efficient dynamic memory managers have been proposed for conventional bus-based MPSoC platforms, there are no DMM solutions regarding the constraints and the opportunities delivered by the physical distribution of multiple memorynodes of the platform. In this work, we address the problem of providing customizedmicrocoded DMM on MPSoC platforms with distributed memory organization. Customization is enabled at application-and platform-level. Results show that customizedmicrocoded DMM can serve approximately 7× more allocation requests compared to puredistributed memory platforms and perform 25% faster than the corresponding high-level implementation in C language. 
  • Aviles, Marcos, et al. (författare)
  • A co-design methodology for implementing computer vision algorithms for rover navigation onto reconfigurable hardware
  • 2011
  • Ingår i: Proceedings of the FPL2011 Workshop on Computer Vision on Low-Power Reconfigurable Architectures. ; s. 9-10
  • Konferensbidrag (övrigt vetenskapligt)abstract
    • Vision-based robotics applications have been widely studied in the last years. However, up to now solutions that have been proposed were affecting mostly software level. The SPARTAN project focuses in the tight and optimal implementation of computer vision algorithms targeting to rover navigation. For evaluation purposes, these algorithms will be implemented with a co-design methodology onto a Virtex-6 FPGA device.
  • Papadopoulos, Lazaros, et al. (författare)
  • A Systematic Methodology for Optimization of Applications Utilizing Concurrent Data Structures
  • 2016
  • Ingår i: IEEE transactions on computers. - 0018-9340. ; 65:7, s. 2019-2031
  • Tidskriftsartikel (refereegranskat)abstract
    • Modern multicore embedded systems often execute applications that rely heavily on concurrent data structures. The selection of efficient concurrent data structure implementations for a specific application is usually a complex and time consuming task, because each design decision often affects the performance and the energy consumption of the embedded system in various and occasionally unpredictable ways. The complexity is normally addressed by developers by adopting ad-hoc design solutions, which are often suboptimal and yield poor results. To face this problem, we propose a semi-automated methodology for the optimization of applications that utilize concurrent data structures that is based on design space exploration. The proposed approach is evaluated by using both microbenchmarks and real-world applications that are executed on multicore embedded systems with different architectural specifications. Our results show that we can identify various trade-offs between different data structure implementations that can be used to optimize applications that rely on concurrent data structures.
  • Papadopoulos, Lazaros, et al. (författare)
  • Performance and power consumption evaluation of concurrent queue implementations in embedded systems
  • 2015
  • Ingår i: Computer Science-Research and Development. - 1865-2034. ; 30:2, s. 165-175
  • Konferensbidrag (refereegranskat)abstract
    • Embedded and high performance computing (HPC) systems face many common challenges. One of them is the synchronization of the memory accesses in shared data. Concurrent queues have been extensively studied in the HPC domain and they are used in a wide variety of HPC applications. In this work, we evaluate a set of concurrent queue implementations in an embedded platform, in terms of execution time and power consumption. Our results show that by taking advantage of the embedded platform specifications, we achieve up to 28.2 % lower execution time and 6.8 % less power dissipation in comparison with the conventional lock-based queue implementation. We show that HPC applications utilizing concurrent queues can be efficiently implemented in embedded systems and that synchronization algorithms from the HPC domain can lead to optimal resource utilization of embedded platforms.
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  • Resultat 1-8 av 8
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