| 1. |
- Howard, Andrew W., et al.
(författare)
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THE NASA-UC ETA-EARTH PROGRAM : I. A SUPER-EARTH ORBITING HD 7924
- 2009
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Ingår i: Astrophysical Journal. - 0004-637X .- 1538-4357. ; 696:1, s. 75-83
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Tidskriftsartikel (refereegranskat)abstract
- We report the discovery of the first low-mass planet to emerge from the NASA-UC Eta-Earth Program, a super-Earth orbiting the K0 dwarf HD 7924. Keplerian modeling of precise Doppler radial velocities reveals a planet with minimum mass M-P sin i = 9.26M(circle plus) in a P = 5.398 d orbit. Based on Keck-HIRES measurements from 2001 to 2008, the planet is robustly detected with an estimated false alarm probability of less than 0.001. Photometric observations using the Automated Photometric Telescopes at Fairborn Observatory show that HD 7924 is photometrically constant over the radial velocity period to 0.19 mmag, supporting the existence of the planetary companion. No transits were detected down to a photometric limit of similar to 0.5 mmag, eliminating transiting planets with a variety of compositions. HD 7924b is one of only eight planets detected by the radial velocity technique with M-P sini < 10 M-circle plus and as such is a member of an emerging family of low-mass planets that together constrain theories of planet formation.
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| 2. |
- Vangal, Sriram, et al.
(författare)
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An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
- 2007
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Ingår i: IEEE International Solid-State Circuits Conference, San Fransisco, USA, 2007. - : IEEE. - 1424408539 ; , s. 98-99
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Konferensbidrag (refereegranskat)abstract
- A 275mm2 network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz. The 15-F04 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. The 65nm 100M transistor die is designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.
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| 3. |
- Vangal, Sriram, et al.
(författare)
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A 5.1GHz 0.34mm2 Router for Network-on-Chip Applications
- 2007
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Ingår i: 2007 IEEE Symposium on VLSI Circuits. - : IEEE. - 9784900784048 - 9784900784055 ; , s. 42-43
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Konferensbidrag (refereegranskat)abstract
- A five-port two-lane pipelined packet-switched router core with phase-tolerant mesochronous links forms the key communication fabric for an 80-tile network-on-chip (NoC) architecture. The 15FO4 design combines 102 GB/s of raw bandwidth with low fall-through latency of 980 ps. A shared crossbar architecture with a double-pumped crossbar switch enables a compact 0.34 mm2 router layout. In a 65nm eight-metal CMOS process, the router contains 210K transistors and operates at 5.1GHz at 1.2 V, while dissipating 945 mW.
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