| 1. |
- Hertz, Erik, 1956-, et al.
(författare)
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A Methodology for parabolic synthesis of unary functions for hardware implementation
- 2008
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Ingår i: SCS 2008. - New York : Institute of Electrical and Electronics Engineers (IEEE). - 9781424426270
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Konferensbidrag (refereegranskat)abstract
- This paper introduces a parabolic synthesis methodology for developing approximations of unary functions like trigonometric functions and logarithms which are specialized for efficient hardware mapped VLSI design. The advantages with the methodology are, short critical path, fast computation and high throughput enabled by a high degree of architectural parallelism. The feasibility of the methodology is shown by developing an approximation of the sine function for implementation in hardware. © 2008 IEEE
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| 2. |
- Hertz, Erik, 1956-, et al.
(författare)
-
Combining the parabolic synthesis methodology with second-degree interpolation
- 2016
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Ingår i: Microprocessors and Microsystems. - Amsterdam : Elsevier BV. - 0141-9331 .- 1872-9436. ; 42, s. 142-155
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Tidskriftsartikel (refereegranskat)abstract
- The Parabolic Synthesis methodology is an approximation methodology for implementing unary functions, such as trigonometric functions, logarithms and square root, as well as binary functions, such as division, in hardware. Unary functions are extensively used in baseband for wireless/wireline communication, computer graphics, digital signal processing, robotics, astrophysics, fluid physics, games and many other areas. For high-speed applications, as well as in low-power systems, software solutions are not sufficient and a hardware implementation is therefore needed. The Parabolic Synthesis methodology is a way to implement functions in hardware based on low complexity operations that are simple to implement in hardware. A difference in the Parabolic Synthesis methodology compared to many other approximation methodologies is that it is a multiplicative, in contrast to additive, methodology. To further improve the performance of Parabolic Synthesis based designs, the methodology is combined with Second-Degree Interpolation. The paper shows that the methodology provides a significant reduction in chip area, computation delay and power consumption with preserved characteristics of the error. To evaluate this, the logarithmic function was implemented, as an example, using the Parabolic Synthesis methodology in comparison to the Parabolic Synthesis methodology combined with Second-Degree Interpolation. To further demonstrate the feasibility of both methodologies, they have been compared with the CORDIC methodology. The comparison is made on the implementation of the fractional part of the logarithmic function with a 15-bit resolution. The designs implemented using the Parabolic Synthesis methodology - with and without the Second-Degree Interpolation - perform 4x and 8x better, respectively, than the CORDIC implementation in terms of throughput. In terms of energy consumption, the CORDIC implementation consumes 140% and 800% more energy, respectively. The chip area is also smaller in the case when the Parabolic Synthesis methodology combined with Second-Degree Interpolation is used.
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| 3. |
- Hertz, Erik, 1956-, et al.
(författare)
-
Parabolic Synthesis Methodology Implemented on the Sine Function
- 2009
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Ingår i: IEEE International Symposium on Circuits and Systems, 2009. ISCAS 2009.. - 9781424438273 ; , s. 253-256
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Konferensbidrag (refereegranskat)abstract
- This paper introduces a parabolic synthesis methodology for implementation of approximations of unary functions like trigonometric functions and logarithms, which are specialized for efficient hardware mapped VLSI design. The advantages with the methodology are, short critical path, fast computation and high throughput enabled by a high degree of architectural parallelism. The feasibility of the methodology is shown by developing an approximation of the sine function for implementation in hardware. ©2009 IEEE.
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| 4. |
- Hertz, Erik, et al.
(författare)
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The Harmonized Parabolic Synthesis Methodology for Hardware Efficient Function Generation with Full Error Control
- 2018
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Ingår i: Journal of Signal Processing Systems. - New York, NY : Springer Science and Business Media LLC. - 1939-8018 .- 1939-8115. ; 90:12, s. 1623-1637
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Tidskriftsartikel (refereegranskat)abstract
- The Harmonized Parabolic Synthesis methodology is a further development of the Parabolic Synthesis methodology for approximation of unary functions such as trigonometric functions, logarithms and the square root with moderate accuracy for ASIC implementation. These functions are extensively used in computer graphics, communication systems and many other application areas. For these high-speed applications, software solutions are not sufficient, and a hardware implementation is therefore needed. The Harmonized Parabolic Synthesis methodology has two outstanding advantages: it is parallel, thus reducing the execution time, and it is based on low complexity operations, thus being simple to implement in hardware. A difference compared to other approximation methodologies is that it is a multiplicative, and not additive, methodology. Compared to the Parabolic Synthesis methodologies it is possible to significantly enhance the performance in terms of reducing chip area, computation delay and power consumption. Furthermore, it increases the possibility to tailor the characteristics of the error, improving conditions for subsequent calculations. To evaluate the methodology, the fractional part of the logarithm is implemented and its performance is compared to the Parabolic Synthesis methodology. The comparison is made with 15-bit resolution. The design implemented using the proposed methodology performs 3× better than the Parabolic Synthesis implementation in terms of throughput, while consuming 90% less energy. The chip area is 70% smaller than for the Parabolic Synthesis methodology. In summary, the new technology further increases the advantages of Parabolic Synthesis.
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| 5. |
- Nilsson, Peter, et al.
(författare)
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Hardware Implementation of the Exponential Function Using Taylor Series
- 2014
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Ingår i: NORCHIP 2014 – 32nd NORCHIP Conference. - Piscataway, NJ : IEEE Press. - 9781479954421
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Konferensbidrag (refereegranskat)abstract
- This paper presents hardware implementations of Taylor series. The focus will be on the exponential function but the methodology is applicable on any unary function. Two different architectures are investigated, one, original, straight forward and one modified structure. The outcomes are higher performance, lower area, and lower power consumption for the modified architecture compared to the original.
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| 6. |
- Nilsson, Peter, et al.
(författare)
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Low Power Unrolled CORDIC Architectures
- 2015
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Ingår i: 2015 Nordic Circuits and Systems Conference (NORCAS). - Piscataway, NJ : IEEE Press. - 9781467365765
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Konferensbidrag (refereegranskat)abstract
- This paper shows a novel methodology to improve unrolled CORDIC architectures. The methodology is based on removing adder stages starting from the first stage. As an example, a 19-stage CORDIC is used but the methodology is applicable on CORDICs with an arbitrary number of stages. The CORDIC is implemented, simulated, and synthesized into hardware. In the paper, the performance is shown to be increased by 23% and that the dynamic power can be reduced by 27%. © 2014 IEEE
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| 7. |
- Nilsson, Peter, et al.
(författare)
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Ultra Low Power Hardware for Computing Squared Euclidean Distances
- 2011
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Ingår i: 2011 20th European Conference on Circuit Theory and Design (ECCTD). - Piscataway, NJ : IEEE Press. - 9781457706172 - 9781457706165 ; , s. 580-583
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Konferensbidrag (refereegranskat)abstract
- Computing Euclidean Distances is a very important operation in digital communication, especially in the case of trellis coded modulation, where it is used numerously. This paper shows that a substantial reduction in complexity can be achieved in hardware processing elements for computing Euclidean Distances. A reduction in complexity down to 39% is shown compared to traditional designs. The paper also shows that the optimized design can be done completely ripple free, which leads to a reduction of the critical path to far more than half. The reduction in complexity leads to a reduction in power consumption. The ripple free design also leads to lower power consumption for two reasons: the rippling in itself leads to unnecessary glitches, which costs power and the shorter critical path enables a lower supply voltage, which reduces the power consumption as well. © 2011 IEEE.
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| 8. |
- Pouyan, Peyman, et al.
(författare)
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A VLSI Implementation of Logarithmic and Exponential Functions Using a Novel Parabolic Synthesis Methodology Compared to the CORDIC Algorithm
- 2011
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Ingår i: 2011 20th European Conference on Circuit Theory and Design (ECCTD). - New York : Institute of Electrical and Electronics Engineers (IEEE). - 9781457706189
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Konferensbidrag (refereegranskat)abstract
- High performance implementations of unary functions are important in many applications e.g. in the wireless communication area. This paper shows the development and VLSI implementation of unary functions like the logarithmic and exponential function, by using anovel approximation methodology based on parabolic synthesis, which is compared to the well known CORDIC algorithm. Both designs are synthesized and implemented on an FPGA and as an ASIC. The results of such implementations are compared with metrics such as performance and area. The performance in the parabolic architecture is shown to exceed the CORDIC architecture by a factor 4.2, in a 65 nm Standard-VT ASIC implementation. © 2011 IEEE.
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