Sök i SwePub databas

  Utökad sökning

Träfflista för sökning "db:Swepub ;pers:(Jantsch Axel);access:(free)"

Sökning: db:Swepub > Jantsch Axel > Fritt online

  • Resultat 1-7 av 7
Sortera/gruppera träfflistan
  • Jantsch, Axel, et al. (författare)
  • Memory Architecture and Management in an NoC Platform
  • 2011
  • Ingår i: Scalable Multi-core Architectures : Design Methodologies and Tools. - Springer. - 9781441967770 ; s. 3-28
  • Bokkapitel (övrigt vetenskapligt)abstract
    • The memory organization and the management of the memory space is a critical part of every NoC based platform design. We propose a Data Management Engine (DME), that is a block of programmable hardware and part of every processing element. It off-loads the processing element (CPU, DSP, etc.) by managing the memory space, memory access and the communication over the on-chip network. The DME’s main functions are virtual address translation, private and shared memory management, cache coherence protocol, support for memory consistency models, synchronization and protection mechanisms for shared memory communication. The DME is fully programmable and configurable thus allowing for customized support for high level data management functions such as dynamic memory allocation and abstract data types. This chapter describes the main concepts, design and functionality of the DME and presents case studies illustrating its usage and performance.
  • Naeem, Abdul, et al. (författare)
  • Architecture Support and Comparison of Three Memory Consistency Models in NoC based Syst
  • 2012
  • Ingår i: Proceedings of 15th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools (DSD 2012). - IEEE Computer Society. - 978-076954798-5 ; s. 304-311
  • Konferensbidrag (refereegranskat)abstract
    • We propose a novel hardware support for three relaxed memory models, Release Consistency (RC), Partial Store Ordering (PSO) and Total Store Ordering (TSO) in Network-on-Chip (NoC) based distributed shared memory multicore systems. The RC model is realized by using a Transaction Counter and an Address Stack based approach while the PSO and TSO models are realized by using a Write Transaction Counter and a Write Address Stack based approach. In the experiments, we use a configurable platform based on a 2D mesh NoC using deflection routing policy. The results show that under synthetic workloads, the average execution time for the RC, PSO and TSO models in 8x8 network (64 cores) is reduced by 35.8%, 22.7% and 16.5% respectively, over the Sequential Consistency (SC) model. The average speedup for the RC, PSO and TSO models in the 8x8 network under different application workloads is increased by 34.3%, 10.6% and 8.9%, respectively, over the SC model. The area cost for the TSO, PSO and RC models is increased by less than 2% over the SC model at the interface to the processor.
  • Naeem, Abdul, et al. (författare)
  • Realization and Performance Comparison of Sequential and Weak Memory Consistency Models in Network-on-Chip based Multi-core Systems
  • 2011
  • Ingår i: Proceedings of 16th ACM/IEEE Asia and South Pacific Design Automation Conference(ASP-DAC) 2011. - IEEE Press. ; s. 154-159
  • Konferensbidrag (refereegranskat)abstract
    • This paper studies realization and performance comparison of the sequential and weak consistency models in the network-on-chip (NoC) based distributed shared memory (DSM) multi-ore systems. Memory consistency constrains the order of shared memory operations for the expected behavior of the multi-core systems. Both the consistency models are realized in the NoC based multi-core systems. The performance of the two consistency models are compared for various sizes of networks using regular mesh topologies and deflection routing algorithm. The results show that the weak consistency improves the performance by 46.17% and 33.76% on average in the code and consistency latencies over the sequential consistency model, due to relaxation in the program order, as the system grows from single core to 64 cores.
  • Naeem, Abdul, et al. (författare)
  • Realization and Scalability of Release and Protected Release Consistency Models in NoC based Systems
  • 2011
  • Ingår i: Proceeding of 14th Euromicro Conference on Digital System Design, 2011. - Oulu : IEEE Computer Society. - 978-1-4577-1048-3 ; s. 47-54
  • Konferensbidrag (refereegranskat)abstract
    • This paper studies the realization and scalability of release and protected release consistency models in Network-on-Chip (NoC) based Distributed Shared Memory (DSM) multi-core systems. The protected release consistency (PRC) model is proposed as an extension of the release consistency (RC) model and provides further relaxation in the shared memory operations. The realization schemes of RC and PRC models use a transaction counter in each node of the NoC based multi-core (McNoC) systems. Further, we study the scalability of these RC and PRC models and evaluate their performance in the McNoC platform. A configurable NoC based platform with 2D mesh topology and deflection routing algorithm is used in the tests. We experiment both with synthetic and application workloads. The performance of the RC and PRC models are compared using sequential consistency (SC) as the baseline. The experiments show that the average code execution time for the PRC model in 8x8 network (64 cores) is reduced by 30.5% over SC, and by 6.5% over RC model. Average data execution time in the 8x8 network for the PRC model is reduced by almost 37% over SC and by 8.8% over RC. The increase in area for the PRC of RC is about 880 gates in the network interface ( 1.7% ).
  • Naeem, Abdul, et al. (författare)
  • Scalability of Relaxed Consistency Models in NoC based Multicore Architectures
  • 2009
  • Ingår i: SIGARCH Computer Architecture News. - ACM Press. - 0163-5964. ; 37:5, s. 8-15
  • Tidskriftsartikel (övrigt vetenskapligt)abstract
    • This paper studies realization of relaxed memory consistency models in the network-on-chip based distributed shared memory (DSM) multi-core systems. Within DSM systems, memory consistency is a critical issue since it affects not only the performance but also the correctness of programs. We investigate the scalability of the relaxed consistency models (weak, release consistency) implemented by using transaction counters. Our experimental results compare the average and maximum code, synchronization and data latencies of the two consistency models for various network sizes with regular mesh topologies. The observed latencies rise for both the consistency models as the network size grows. However, the scaling behaviors are different. With the release consistency model these latencies grow significantly slower than with the weak  onsistency due to better optimization potential by means of overlapping, reordering and program order relaxations. The release consistency improves the performance by 15.6% and 26.5% on average in the code and consistency latencies over the weak consistency model for the specific application, as the system grows from single core to 64 cores. The latency of data transactions  rows 2.2 times faster on the average with a weak consistency model than with a release consistency model when the system scales from single core to 64 cores.
  • She, Huimin, et al. (författare)
  • Modeling and Analysis of Rayleigh Fading Channels using Stochastic Network Calculus
  • 2011
  • Konferensbidrag (refereegranskat)abstract
    • Deterministic network calculus (DNC) is not suitable for deriving performance guarantees for wireless networks due to their inherently random behaviors. In this paper, we develop a method for Quality of Service (QoS) analysis of wireless channels subject to Rayleigh fading based on stochastic network calculus. We provide closed-form stochastic service curve for the Rayleigh fading channel. With this service curve, we derive stochastic delay and backlog bounds. Simulation results verify that the bounds are reasonably tight. Moreover, through numerical experiments, we show the method is not only capable of deriving stochastic performance bounds, but also can provide guidelines for designing transmission strategies in wireless networks.
  • Thid, Rikard, et al. (författare)
  • Evaluating NoC communication backbones with simulation
  • 2003
  • Ingår i: Proceedings of the 21th NorChip Conference. - IEEE conference proceedings. ; s. 27-30
  • Konferensbidrag (refereegranskat)abstract
    • This paper describes a Network on Chip simulatorthat was developed to evaluate our NoC architecture Nostrum.It is shown how SystemC’s features for communicationrefinement is used to make a highly flexible simulator.The simulator is reconfigurable so that it is possibleto try different NoC platforms and different mappingsof workloads. In addition to the modeling of our Nostrumarchitecture, a bus-based architecture is modeled aswell, and the performance for a simple workload modelis compared.
Skapa referenser, mejla, bekava och länka
  • Resultat 1-7 av 7
pil uppåt Stäng

Kopiera och spara länken för att återkomma till aktuell vy