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1.
  • Al-Khatib, Iyad, et al. (författare)
  • A Multiprocessor System-on-Chip for Real-Time Biomedical Monitoring and Analysis : Architectural Design Space Exploration
  • 2006
  • Ingår i: DAC '06 : Proceedings of the 43rd annual Design Automation Conference. ; s. 125-130
  • Konferensbidrag (refereegranskat)abstract
    • In this paper we focus on MPSoC architectures for human heart ECGreal-time monitoring and analysis. This is a very relevant bio-medicalapplication, with a huge potential market, hence it is an ideal targetfor an application-specific SoC implementation. We investigate asymmetric multi-processor architecture based on STMicroelectronicsVLIW DSPs that process in real-time 12-lead ECG signals. Thisarchitecture improves upon state-of-the-art SoC designs for ECGanalysis in its ability to analyze the full 12 leads in real-time, evenwith high sampling frequencies, and ability to detect heartmalfunction. We explore the design space by considering a number ofhardware and software architectural options.
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2.
  • Al Khatib, Iyad, et al. (författare)
  • ECG-BIONET : A global biomedical network for human heart monitoring and analysis: Performance needs of an electrocardiogram Telemedicine platform for medical aid at the point-of-need
  • 2006
  • Ingår i: 25TH IEEE INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATIONS : VOLS 1-7, PROCEEDINGS IEEE INFOCOM 2006. - New York : IEEE. - 978-1-4244-0221-2 ; s. 3282-3283
  • Konferensbidrag (refereegranskat)abstract
    • In this paper, we propose a Tele-medicine application platform as a medical aid for patients suffering from Heart malfunction. We focus on heart diseases since they remain by far the major cause of death in the globe. Our solution utilizes the Satellite communication protocol DVB-RCS (Digital Video Broadcast- Return Channel Satellite), Wi-Fi, and the Network-on-Chip (NoC) technology. We utilize the 12-lead ECG biomedical technique to detect heart disorders via the biomedical NoC, which transmits the medical alarm and results via the biomedical network, ECG-BIONET. We do not investigate the DVB-RCS standard or Wi-Fi technology, but rather we try to utilize this technology, and we look at it from a performance point of view for our application by investigating three parameters, namely: delay, packet loss, and reliability. We follow a top down approach by looking at the needs of the application from a performance guarantee for our specific-purpose network.
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3.
  • Al Khatib, Iyad, et al. (författare)
  • Hardware/Software architecture for real-time ECG monitoring and analysis leveraging MPSoC technology
  • 2007
  • Ingår i: Transactions on High-Performance Embedded Architectures and Compilers I. - 978-3-540-71527-6 ; s. 239-258
  • Konferensbidrag (refereegranskat)abstract
    • The interest in high performance chip architectures for biomedical applications is gaining a lot of research and market interest. Heart diseases remain by far the main cause of death and a challenging problem for biomedical engineers to monitor and analyze. Electrocardiography (ECG) is an essential practice in heart medicine. However, ECG analysis still faces computational challenges, especially when 12 lead signals are to be analyzed in parallel, in real time, and under increasing sampling frequencies. Another challenge is the analysis of huge amounts of data that may grow to days of recordings. Nowadays, doctors use eyeball monitoring of the 12-lead ECG paper readout, which may seriously impair analysis accuracy. Our solution leverages the advance in multi-processor system-on-chip architectures, and it is centered on the parallelization of the ECG computation kernel. Our Hardware- Software (HW/SW) Multi-Processor System-on-Chip (MPSoQ design improves upon state-of-the-art mostly for its capability to perform real-time analysis of input data, leveraging the computation horsepower provided by many concurrent DSPs, more accurate diagnosis of cardiac diseases, and prompter reaction to abnormal heart alterations. The design methodology to go from the 12-lead ECG application specification to the final HW/SW architecture is the focus of this paper. We explore the design space by considering a number of hardware and software architectural variants, and deploy industrial components to build up the system.
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4.
  • Al-Khatib, Iyad, et al. (författare)
  • Performance Analysis and Design Space Exploration for High-End Biomedical Applications : Challenges and Solutions
  • 2007
  • Ingår i: Proceedings of the International Conference on Hardware - Software Codesign and System Synthesis. - 978-159593824-4 ; s. 217-226
  • Konferensbidrag (refereegranskat)abstract
    • High-end biomedical applications are a good target for specific-purpose system-on-chip (SoC) implementations. Human heart electrocardiogram (ECG) real-time monitoring andanalysis is an immediate example with a large potential market. Today, the lack of scalable hardware platforms limits real-time analysis capabilities of most portable ECG analyzers, and prevents the upgrade of analysis algorithms for better accuracy. Multiprocessor system-on-chip (MPSoC) technology, which is becoming main-stream in the domain of high-performance microprocessors, is becoming attractive even for power-constrained portable applications, due to the capability to provide scalable computation horsepower at an affordable power cost. This paper illustrates one of the first comprehensive HW/SW exploration frameworks to fully exploit MPSoC technology to improve the quality of real-time ECG analysis.
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5.
  • Anagnostopoulos, Iraklis, et al. (författare)
  • Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations
  • 2011
  • Ingår i: IEEE Embedded Systems Letters. - 1943-0663. ; 3:2, s. 66-69
  • Tidskriftsartikel (refereegranskat)abstract
    • Multiprocessor system-on-chip (MPSoCs) have attracted significant attention since they are recognized as a scalable paradigm to interconnect and organize a high number of cores. Current multicore embedded systems exhibit increased levels of dynamicbehavior, leading to unexpected memory footprint variations unknown at design time.Dynamic memory management (DMM) is a promising solution for such types of dynamicsystems. Although some efficient dynamic memory managers have been proposed for conventional bus-based MPSoC platforms, there are no DMM solutions regarding the constraints and the opportunities delivered by the physical distribution of multiple memorynodes of the platform. In this work, we address the problem of providing customizedmicrocoded DMM on MPSoC platforms with distributed memory organization. Customization is enabled at application-and platform-level. Results show that customizedmicrocoded DMM can serve approximately 7× more allocation requests compared to puredistributed memory platforms and perform 25% faster than the corresponding high-level implementation in C language. 
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6.
  • Badlund, Per, et al. (författare)
  • An analytical approach for dimensioning mixed traffic networks
  • 2007
  • Ingår i: NOCS 2007 : First International Symposium on Networks-on-Chip, Proceedings. - 978-0-7695-2773-4 ; s. 215-215
  • Konferensbidrag (refereegranskat)abstract
    • We present an analytical method for analyzing and dimensioning a network based communication architecture. The method is based on the classic (a, p) network calculus. We use a TDMA approach for creating logically separated networks which makes statistical methods possible for calculations on Best Effort traffic, and supports implementation of Guaranteed Bandwidth services by using Virtual Circuits with Looped Containers.
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