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Sökning: db:Swepub > Jantsch Axel > Engelska > Liu Ming > Refereegranskat

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1.
  • Liu, Ming, et al. (författare)
  • A High-End Reconfigurable Computation Platform for Nuclear and Particle Physics Experiments
  • 2011
  • Ingår i: Computing in science & engineering (Print). - 1521-9615. ; 13:2, s. 52-63
  • Tidskriftsartikel (refereegranskat)abstract
    • A high-performance computation platform based on field-programmable gate arrays targets nuclear and particle physics experiment applications. The system can be constructed or scaled into a supercomputer-equivalent size for detector data processing by inserting compute nodes into advanced telecommunications computing architecture (ATCA) crates. Among the case study results are that one ATCA crate can provide a computation capability equivalent to hundreds of commodity PCs for Hades online particle track reconstruction and Cherenkov ring recognition.
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2.
  • Liu, Ming, et al. (författare)
  • A Reconfigurable Design Framework for FPGA Adaptive Computing
  • 2009
  • Ingår i: 2009 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS. - IEEE. - 978-1-4244-5293-4 ; s. 439-444
  • Konferensbidrag (refereegranskat)abstract
    • Partial Reconfiguration (PR) offers the possibility to adaptively change part of the FPGA design without stopping the remaining system. In this paper, we present a comprehensive framework for adaptive computing, in which design key points of hardware processes, system interconnections, Operating Systems (OS), device drivers, scheduler software as well as context switching are respectively concerned in different hardware/software layers. A case study is discussed to demonstrate an example of swapping a Flash memory controller and an SRAM controller in response to diverse memory access needs. Result analysis reveals a more efficient resource utilization of 52.1% I/O pads, 86.5% LUTs and 81.3% Flip-Flops, when compared to the static design with same functionalities. A small reconfiguration overhead of context switching is measured within the range from hundreds of microseconds to milliseconds. Moreover, technical perspectives are analyzed and it is foreseen to obtain great benefits with the proposed design framework in object applications of particle physics experiments.
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3.
  • Liu, Ming, et al. (författare)
  • ATCA-based Computation Platform for Data Acquisition and Triggering in Particle Physics Experiments
  • 2008
  • Ingår i: 2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2. ; s. 287-292
  • Konferensbidrag (refereegranskat)abstract
    • An ATCA-based computation platform for data acquisition and trigger applications in nuclear and particle physics experiments has been developed. Each Compute Node (CN) which appears as a Field Replaceable Unit (FRU) in an ATCA shelf, features 5 Xilinx Virtex-4 FX60 FPGAs and up to 10 GBytes DDR2 memory. Connectivity is provided with 8 optical links and 5 Gigabit Ethernet ports, which are mounted on each board to receive data from detectors and forward results to outer shelves or PC farms with attached mass storage. Fast point-to-point on-board interconnections between FPGAs as well as the full-mesh shelf backplane provide flexibility and high bandwidth to partition algorithms and correlate results among them. The system represents a highly reconfigurable and scalable solution for multiple applications.
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4.
  • Liu, Ming, et al. (författare)
  • FPGA-based adaptive computing for correlated multi-stream processing
  • 2010
  • Ingår i: Proceedings -Design, Automation and Test in Europe, DATE. - IEEE Computer Society. - 978-398108016-2 ; s. 973-976
  • Konferensbidrag (refereegranskat)abstract
    • In conventional static implementations for correlated streaming applications, computing resources may be inefficiently utilized since multiple stream processors may supply their sub-results at asynchronous rates for result correlation or synchronization. To enhance the resource utilization efficiency, we analyze multi-streaming models and implement an adaptive architecture based on FPGA Partial Reconfiguration (PR) technology. The adaptive system can intelligently schedule and manage various processing modules during run-time. Experimental results demonstrate up to 78.2% improvement in throughput-per-unit- area on unbalanced processing of correlated streams, as well as only 0.3% context switching overhead in the overall processing time in the worst-case.
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5.
  • Liu, Ming, et al. (författare)
  • FPGA-based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments
  • 2011
  • Ingår i: Reconfigurable Computing : Architectures, Tools And Applications. - Springer. - 978-3-642-19474-0 ; s. 169-180
  • Konferensbidrag (refereegranskat)abstract
    • Cherenkov ring is often adopted to identify particles flying through the detector systems in nuclear and particle physics experiments. In this paper, we introduce an improved ring recognition algorithm and present its FPGA implementation. Compared to the previous implementation based on VMEBus and FPGAs, our design is evaluated to outperform by several tens up to hundred times with acceptable resource utilizations on a Xilinx Virtex-4 FX60 FPGA. The design module will reside in the online data acquisition (DAQ) and trigger facilities, and contribute to significantly reduce the data rate of storage for offline analysis by retaining only interesting events and dropping the noise. Our customized FPGA cluster in one ATCA [1] shelf is foreseen to achieve an equivalent computation capability up to thousands of commodity PCs for particle recognition.
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7.
  • Liu, Ming, et al. (författare)
  • Hardware/Software co-design of a general-purpose computation platform in particle physics
  • 2007
  • Ingår i: ICFPT 2007 : International Conference On Field-Programmable Technology, Proceedings. - 978-1-4244-1471-0 ; s. 177-183
  • Konferensbidrag (refereegranskat)abstract
    • In this paper we present a hardware/software co-design based computation platform for online data processing in particle physics experiments. Our goal is to ease and accelerate the development and make it universal and scalable for multiple applications, on the premise of guaranteeing high communicating and processing capabilities. The entire computation network consists of quite a few interconnected compute nodes, each of which has multiple FPGAs to implement specific algorithms for data processing. High-speed communication features including RocketIO multi-gigabit transceiver and Gigabit Ethernet are supported by FPGAs to construct internal and external connections. An embedded Linux operating system is fitted on the PowerPC CPU core inside the Xilinx Virtex-4 FX FPGA. Thus programmers can access hardware resources via device drivers and write application programs to manage the system from the high level. Furthermore measurements have been executed using the development board to investigate both communicating and processing performances of the system. Results show that the computation platform is able to communicate at a UDP/IP data rate of around 400 Mbps per Ethernet link, and the event selection engine could process an event rate of 25%.
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8.
  • Liu, Ming, et al. (författare)
  • Inter-process communication using pipes in FPGA-based adaptive computing
  • 2010
  • Ingår i: Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010. - 978-076954076-4 ; s. 80-85
  • Konferensbidrag (refereegranskat)abstract
    • In FPGA-based adaptive computing, Inter-Process Communications (IPC) are required to exchange information among hardware processes which time-multiplex the resources in a same reconfigurable region. In this paper, we use pipes for IPC and analyze the performance in terms of throughput, throughput efficiency and latency in switching contexts. We also present two practical implementations using FPGA BRAM and external DDR memory. Experimental results expose the key role that context switching plays in determining the IPC performance at various pipe sizes and data rates.
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9.
  • Liu, Ming, et al. (författare)
  • Reducing FPGA Reconfiguration Time Overhead using Virtual Configurations
  • 2010
  • Ingår i: Proceedings of the 5th International Workshop on Reconfigurable Communication Centric Systems-on-Chip.
  • Konferensbidrag (refereegranskat)abstract
    • Reconfiguration time overhead is a critical factor in determining the system performance of FPGA dynamically reconfigurable designs. To reduce the reconfiguration overhead, the most straightforward way is to increase the reconfiguration throughput, as many previous contributions did. In addition to shortening FPGA reconfiguration time, we introduce a new concept of Virtual ConFigurations (VCF) in this paper, hiding dynamic reconfiguration time in the background to reduce the overhead. Experimental results demonstrate up to 29.9% throughput enhancement by adopting two VCFs in a consumerreconfigurable design. The packet latency performance is also largely improved by extending the channel saturation to a higher packet injection rate.
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10.
  • Liu, Ming, et al. (författare)
  • Run-time Partial Reconfiguration Speed Investigation and Architectural Design Space Exploration
  • 2009
  • Ingår i: FPL 09 : 19th International Conference on Field Programmable Logic and Applications. - 978-1-4244-3891-4 ; s. 498-502
  • Konferensbidrag (refereegranskat)abstract
    • Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Access (DMA), Master (MST) burst, and a dedicated Block RAM (BRAM) cache respectively to reduce the reconfiguration time. Based on the Xilinx PR technology and the Internal Configuration Access Port (ICAP) primitive in the FPGA fabric, we discuss multiple design architectures and thoroughly investigate their performance with measurements for different partial bitstream sizes. Compared to the reference OPB_HWICAP and XPS_HWICAP designs, experimental results show that DMA_HWICAP and MST_HWICAP reduce the reconfiguration time by one order of magnitude, with little resource consumption overhead. The BRAM_HWICAP design can even approach the reconfiguration speed limit of the ICAP primitive at the cost of large Block RAM utilization.
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