| 1. |
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| 2. |
- Lee, S. -K, et al.
(författare)
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Reduction of the barrier height and enhancement of tunneling current of titanium contacts using embedded Au nano-particles on 4H and 6H silicon carbide
- 2002
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Ingår i: Materials Science Forum. - : Trans Tech Publications Inc.. - 0255-5476 .- 1662-9752. ; 389-393:2, s. 937-940
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Tidskriftsartikel (refereegranskat)abstract
- We have investigated the electrical characteristics of Ti Schottky contacts with embedded Au nano-particles on various types of epilayers of SiC (4H- and 6H-SiC). From our current-voltage (I-V) and capacitance-voltage (C-V) measurements, we observed that Ti Schottky contacts with embedded Au nano-particles had 0.19 eV (n-4H-SiC) and 0.15 eV (n-6H-SiC) lower barrier height than those of particle free Ti Schottky contacts. In order to understand this reduction of the Schottky barrier height (SBH) for Ti Schottky contacts with embedded Au nano-particles, it has been proposed that SBH lowering is caused by an enhanced electric field due to the small size of the Au nano-particles and the large SBH difference. We have also tested these contacts on highly doped n-and p-type SiC material to study ohmic contacts using linear TLM measurements.
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| 3. |
- Persson, Stefan, et al.
(författare)
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Strained-Silicon Heterojunction Bipolar Transistor
- 2010
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 57:6, s. 1243-1252
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Tidskriftsartikel (refereegranskat)abstract
- Experimental and modeling results are reported for high-performance strained-silicon heterojunction bipolar transistors (HBTs), comprising a tensile strained-Si emitter and a compressively strained Si0.7Ge0.3 base on top of a relaxed Si0.85Ge0.15 collector. By using a Si0.85Ge0.15 virtual substrate strain platform, it is possible to utilize a greater difference in energy band gaps between the base and the emitter without strain relaxation of the base layer. This leads to much higher gain, which can be traded off against lower base resistance. There is an improvement in the current gain beta of 27x over a conventional silicon bipolar transistor and 11x over a conventional SiGe HBT, which were processed as reference devices. The gain improvement is largely attributed to the difference in energy band gap between the emitter and the base, but the conduction band offset between the base and the collector is also important for the collector current level.
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| 4. |
- Hellström, Per-Erik, et al.
(författare)
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Integration of Silicon Nanowires with CMOS
- 2014
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Ingår i: Beyond CMOS Nanodevices 1. - Hoboken, NJ, USA : Wiley Blackwell. - 9781118984772 - 9781848216549 ; , s. 65-72
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Bokkapitel (övrigt vetenskapligt/konstnärligt)abstract
- Silicon nanowires exhibit attractive characteristics that have motivated their use as the sensor element in a biochemical sensor system. An integrated silicon nanowire and complementary metal-oxide-semiconductor (CMOS) circuit chip would allow more design freedom with respect to interaction with the full biochemical sensor system, including interaction with the electrolyte solution. The CMOS fabrication process is divided into two parts, called the front-end-of-line (FEOL) and back-end-of-line (BEOL) processing. A CMOS process that allows the integration of silicon nanowires, as described in this chapter offers a vast amount of design opportunities to enhance the performance of the silicon nanowire-based sensor. The chapter describes a sensor design that allows measurement of the conductance variations of biosensitive silicon nanowires in a serial manner by using on-chip integrated CMOS circuitry. Integration of silicon nanowires can also be achieved by defining the silicon nanowires in the silicon layer of a SOI wafer.
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| 5. |
- A. M. Naiini, Maziar, 1980-
(författare)
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Horizontal Slot Waveguides for Silicon Photonics Back-End Integration
- 2014
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- This thesis presents the development of integrated silicon photonic devices. These devices are compatible with the present and near future CMOS technology. High-khorizontal grating couplers and waveguides are proposed. This work consists of simulations and device design, as well as the layout for the fabrication process, device fabrication, process development, characterization instrument development and electro-optical characterizations.The work demonstrates an alternative solution to costly silicon-on-insulator photonics. The proposed solution uses bulk silicon wafers and thin film deposited waveguides. Back-end deposited horizontal slot grating couplers and waveguides are realized by multi-layers of amorphous silicon and high-k materials.The achievements of this work include: A theoretical study of fully etched slot grating couplers with Al2O3, HfO2 and AIN, an optical study of the high-k films with spectroscopic ellipsometry, an experimental demonstration of fully etched SiO2 single slot grating couplers and double slot Al2O3 grating couplers, a practical demonstration of horizontal double slot high-k waveguides, partially etched Al2O3 single slot grating couplers, a study of a scheme for integration of the double slot Al2O3 waveguides with selectively grown germanium PIN photodetectors, realization of test chips for the integrated germanium photodetectors, and study of integration with graphene photodetectors through embedding the graphene into a high-k slot layer.From an application point of view, these high-k slot waveguides add more functionality to the current silicon photonics. The presented devices can be used for low cost photonics applications. Also alternative optical materials can be used in the context of this photonics platform.With the robust design, the grating couplers result in improved yield and a more cost effective solution is realized for integration of the waveguides with the germanium and graphene photodetectors.
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| 6. |
- Abedin, Ahmad, 1984-
(författare)
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Germanium layer transfer and device fabrication for monolithic 3D integration
- 2021
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Monolithic three-dimensional (M3D) integration, it has been proposed,can overcome the limitations of further circuits’ performance improvementand functionality expansion. The emergence of the internet of things (IoT) isdriving the semiconductor industry toward the fabrication of higher-performancecircuits with diverse functionality. On the one hand, the scaling of devices isreaching critical dimensions, which makes their further downscaling techno-logically difficult and economically challenging, whereas, on the other hand,the field of electronics is no longer limited only to developing circuits thatare meant for data processing. Sensors, processors, actuators, memories, andeven power storage units need to be efficiently integrated into a single chip tomake IoT work. M3D integration through stacking different layers of deviceson each other can potentially improve circuits’ performance by shorteningthe wiring length and reducing the interconnect delay. Using multiple tiersfor device fabrication makes it possible to integrate different materials withsuperior physical properties. It offers the advantage of fabricating higher-performance devices with multiple functionalities on a single chip. However,high-quality layer transfer and processing temperature budget are the majorchallenges in M3D integration. This thesis involves an in-depth explorationof the application of germanium (Ge) in monolithic 3D integration.Ge has been recognized as one of the most promising materials that canreplace silicon (Si) as the channel material for p-type field-effect transistors(pFETs) because of its high hole mobility. Ge pFETs can be fabricated atsubstantially lower temperatures compared to Si devices which makes theformer a good candidate for M3D integration. However, the fabrication ofhigh-quality Ge-on-insulator (GOI) layers with superior thickness homogene-ity, low residual doping, and a sufficiently good interface with buried oxide(BOX) has been challenging.This thesis used low-temperature wafer bonding and etch-back techniquesto fabricate the GOI substrate for M3D applications. For this purpose, aunique stack of epitaxial layers was designed and fabricated. The layer stackcontains a Ge strain relaxed buffer (SRB) layer, a SiGe layer to be used asan etch stop, and a top Ge layer to be transferred to the handling wafer.The wafers were bonded at room temperature, and the sacrificial wafer wasremoved through multiple etching steps leaving 20 nm Ge on the insulatorwith excellent thickness homogeneity over the wafer. Ge pFET devices werefabricated on the GOI substrates and electrically characterized to evaluatethe layer quality. Finally, the epitaxial growth of the highly doped SiGeand sub-nm Si cap layers have been investigated as alternatives for improvedperformance Ge pFETs.The Ge buffer layer was developed through the two-step deposition tech-nique resulting in defect density of107cm−3and surface roughness of 0.5 nm.The fully strainedSi0.5Ge0.5film with high crystal quality was epitaxiallygrown at temperatures below 450°C. The layer was sandwiched between theGe buffer and the top 20 nm Ge layer to be used as an etch-stop in the etch- back process. A highly selective etching method was developed to remove the3μm Ge buffer and 10nm SiGe film without damaging the 20 nm transferringGe layer.The Ge pFETs were fabricated at temperatures below 600°C so that theycould be compatible with the M3D integration. The back interface of thedevices depleted atVBG= 0V, which confirmed the small density of fixedcharges at the Ge/BOX interface along with a low level of residual doping inthe Ge channel. The Ge pFETs with 70 % yield over the whole wafer showed60 % higher carrier mobility than Si reference devices.Low-temperature epitaxial growth of Si passivation layer on Ge was de-veloped in this thesis. For electrical evaluation of the passivation layer,metal-oxide-semiconductor (MOS) capacitors were fabricated and character-ized. The capacitors showed an interface trap density of3×1011eV−1cm−2,and hysteresis as low as 3 mV at Eox of 4MV/cm corresponding to oxide trapdensity of1.5×1010cm−2. The results indicate that this Si passivation layersubstantially improves the gate dielectric by reducing the subthreshold slopeof Ge devices while increasing their reliability. The in-situ doped SiGe layerwith a dopant concentration of2.5×1019cm−3and resistivity of 3.5 mΩcmwas selectively grown on Ge to improve the junction formation.The methods developed in this thesis are suitable for large-scale M3Dintegration of Ge pFET devices on the Si platform. The unique Ge layertransfer and etch-back techniques resulted in the fabrication of GOI substrateswith high thickness homogeneity, low residual doping, and sufficiently goodGe/BOX interface. The process temperatures for Ge transfer and pFETsfabrication are kept within the range of the M3D budget. Integration of theSi cap for gate dielectric formation and SiGe layers in the source/drain regionmay increase device performance and reliability
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| 7. |
- Balestra, F., et al.
(författare)
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NANOSIL network of excellence-silicon-based nanostructures and nanodevices for long-term nanoelectronics applications
- 2008
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Ingår i: Materials Science in Semiconductor Processing. - : Elsevier BV. - 1369-8001 .- 1873-4081. ; 11:5-6, s. 148-159
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Tidskriftsartikel (refereegranskat)abstract
- NANOSIL Network of Excellence [NANOSIL NoE web site < www.nanosil-noe.eu >], funded by the European Commission in the 7th Framework Programme (ICT-FP7, no 216171), aims at European scale integration of the excellent European research laboratories and their capabilities in order to strengthen scientific and technological excellence in the field of nanoelectronic materials and devices for terascale integrated circuits (ICs), and to disseminating the results in a wide scientific and industrial community. NANOSIL is exploring and assessing the science and technological aspects of nanodevices and operational regimes relevant to the n+4 technology node and beyond. It encompasses projects on nanoscale CMOS and beyond-CMOS. Innovative concepts, technologies and device architectures are proposed-with fabrication down to the finest features, and utilising a wide spectrum of advanced deposition and processing capabilities, extensive characterization and very rigorous device modeling. This work is carried out through a network of joint processing, characterization and modeling platforms. This critical interaction strengthens European integration in nanoelectronics and will speed up technological innovation for the nanoelectronics of the next two to three decades.
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| 8. |
- Bolten, J., et al.
(författare)
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Fabrication of Nanowires
- 2014
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Ingår i: Beyond CMOS Nanodevices 1. - Hoboken, NJ, USA : Wiley Blackwell. - 9781118984772 - 9781848216549 ; , s. 5-23
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Bokkapitel (övrigt vetenskapligt/konstnärligt)abstract
- Several fabrication processes of silicon nanowires have been developed in the research community. They can be divided into bottom-up or top-down approaches. This chapter describes top-down fabrication of silicon nanowires using electron beam lithography (EBL), which combined with optical lithography can be a viable approach if not too many silicon nanowires need to be patterned on a wafer. It also describes the sidewall transfer lithography (STL) technique using I-line stepper lithography to pattern a vast amount of silicon nanowires on a silicon wafer. In addition the chapter examines how bottom-up Si nanowires synthesized by vapor-liquid-solid (VLS)-chemical vapor deposition (CVD) can be assembled at low cost in an efficient way for further use as a sensing material. Among the solution-based assembly methods for the nanostructured network (nanonet) fabrication, the vacuum filtration method is highly simple, versatile, low cost and scalable to large areas.
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| 9. |
- Buono, Benedetto, et al.
(författare)
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Current Gain Degradation in 4H-SiC Power BJTs
- 2011
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Ingår i: Materials Science Forum. - : Trans Tech Publications Inc.. - 0255-5476 .- 1662-9752. ; 679-680, s. 702-705
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Tidskriftsartikel (refereegranskat)abstract
- SiC airs are very attractive for high power application, but long term stability is still problematic and it could prohibit commercial production of these devices. The aim of this paper is to investigate the current gain degradation in BJTs with no significant degradation of the on-resistance. Electrical measurements and simulations have been used to characterize the behavior of the BJT during the stress test. Current gain degradation occurs, the gain drops from 58 before stress to 43 after 40 hours, and, moreover, the knee current shows fluctuations in its value during the first 20 hours. Current gain degradation has been attributed to increased interface traps or reduced lifetime in the base-emitter region or small stacking faults in the base-emitter region, while fluctuations of the knee current might be due to stacking faults in the collector region.
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| 10. |
- Buono, Benedetto
(författare)
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Simulation and Characterization of Silicon Carbide Power Bipolar Junction Transistors
- 2012
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The superior characteristics of silicon carbide, compared with silicon, have suggested considering this material for the next generation of power semiconductor devices. Among the different power switches, the bipolar junction transistor (BJT) can provide a very low forward voltage drop, a high current capability and a fast switching speed. However, in order to compete on the market, it is crucial to a have high current gain and a breakdown voltage close to ideal. Moreover, the absence of conductivity modulation and long-term stability has to be solved. In this thesis, these topics are investigated comparing simulations and measurements. Initially, an efficient etched JTE has been simulated and fabricated. In agreement with the simulations, the fabricated diodes exhibit the highest BV of around 4.3 kV when a two-zone JTE is implemented. Furthermore, the simulations and measurements demonstrate a good agreement between the electric field distribution inside the device and the optical luminescence measured at breakdown. Additionally, an accurate model to simulate the forward characteristics of 4H-SiC BJTs is presented. In order to validate the model, the simulated current gains are compared with measurements at different temperatures and different base-emitter geometries. Moreover, the simulations and measurements of the on-resistance are compared at different base currents and different temperatures. This comparison, coupled with a detailed analysis of the carrier concentration inside the BJT, indicates that internal forward biasing of the base-collector junction limits the BJT to operate at high current density and low forward voltage drop simultaneously. In agreement with the measurements, a design with a highly-doped extrinsic base is proposed to alleviate this problem. In addition to the static characteristics, the comparison of measured and simulated switching waveforms demonstrates that the SiC BJT can provide fast switching speed when it acts as a unipolar device. This is crucial to have low power losses during transient. Finally, the long-term stability is investigated. It is observed that the electrical stress of the base-emitter diode produces current gain degradation; however, the degradation mechanisms are still unclear. In fact, the analysis of the measured Gummel plot suggests that the reduction of the carrier lifetime in the base-emitter region might be only one of the causes of this degradation. In addition, the current gain degradation due to ionizing radiation is investigated comparing the simulations and measurements. The simulations suggest that the creation of positive charge in the passivation layer can increase the base current; this increase is also observed in the electrical measurements.
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