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Per-flow delay boun...
Per-flow delay bound analysis based on a formalized microarchitectural model
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- Zhao, Xueqian (författare)
- KTH,Elektroniksystem
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- Lu, Zhonghai (författare)
- KTH,Elektroniksystem
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(creator_code:org_t)
- IEEE, 2013
- 2013
- Engelska.
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Ingår i: 2013 7th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2013. - : IEEE. - 9781467364928 ; , s. 6558411-
- Relaterad länk:
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https://urn.kb.se/re...
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visa fler...
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https://doi.org/10.1...
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Abstract
Ämnesord
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- System design starting from high level models can facilitate formal verification of system properties, such as safety and deadlock freedom. Yet, analyzing their QoS property, in our context, per-flow delay bound, is an open challenge. Based on xMAS (eXecutable Micro-Architectural Specification), a formal framework modeling communication fabrics, we present a QoS analysis procedure using network calculus. Given network and flow knowledge, we first create a well-defined xMAS model for a specific application on a concrete on-chip network. Then the specific xMAS model can be mapped to its network calculus analysis model for which existing QoS analysis techniques can be applied to compute end-to-end delay bound per flow. We give an example to show the step-by-step analysis procedure and discuss the tightness of the results.
Nyckelord
- Deadlock freedom
- End-to-end delay bounds
- Formal framework
- Formal verifications
- High-level models
- Network calculus
- On-chip networks
- Step-by-step analysis
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