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Power analysis for ...
Power analysis for Asynchronous CLICH Network-on-Chip
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Ghany, M. A. A. E. (författare)
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Reehal, G. (författare)
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Korzec, D. (författare)
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- Ismail, Mohammed (författare)
- KTH,Integrerade komponenter och kretsar,Ohio State University, Columbus, United States,RaMSiS Group
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(creator_code:org_t)
- IEEE, 2010
- 2010
- Engelska.
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Ingår i: Proceedings - IEEE International SOC Conference, SOCC 2010. - : IEEE. - 9781424466832 ; , s. 499-504
- Relaterad länk:
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https://urn.kb.se/re...
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https://doi.org/10.1...
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Abstract
Ämnesord
Stäng
- Asynchronous Chip-Level Integration of Communicating Heterogeneous Elements (CLICH) architecture is proposed to achieve low power Network-on-Chip (NoC). Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfer between two switches ( data satisfies a certain condition. The area of Asynchronous CLICH switch is increased by 25% as compared to the Synchronous switch. However, the power dissipation of the Asynchronous architecture could be decreased by 21% as compared to the power dissipation in the conventional Synchronous architecture when the ( data equals 0.2 and the activity factor of the control signals is equal to 1 over 64 of the ( data. The total metal resources required to implement Asynchronous design is decreased by 7%.
Ämnesord
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Nyckelord
- CLICH
- GALS
- Low Power
- NoC
Publikations- och innehållstyp
- ref (ämneskategori)
- kon (ämneskategori)
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