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Exploring stacked m...
Exploring stacked main memory architecture for 3D GPGPUs
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- Zhang, Yuang (författare)
- KTH,Elektroniksystem
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Li, L. (författare)
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Jantsch, A. (författare)
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- Lu, Zhonghai (författare)
- KTH,Elektronik och Inbyggda System
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Gao, M. (författare)
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Fu, Y. (författare)
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Pan, H. (författare)
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(creator_code:org_t)
- IEEE conference proceedings, 2015
- 2015
- Engelska.
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Ingår i: Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. - : IEEE conference proceedings. - 9781479984831
- Relaterad länk:
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http://ieeexplore.ie...
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https://urn.kb.se/re...
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https://doi.org/10.1...
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Abstract
Ämnesord
Stäng
- The tremendous number of threads on general purpose graphic processing units (GPGPUs) poses significant challenges on memory architecture design. 3D stacked main memory architecture atop GPGPU is a potential approach to provide high data communication bandwidth and low access latency to meet the requirement of GPGPUs. In this paper, we explore the performance of 3D GPGPUs with stacked main memory. The experimental results show that the 3D stacked GPGPU can provide up to 124.1% and on average 55.8% performance improvement compared to a 2D GPGPU scheme.
Ämnesord
- NATURVETENSKAP -- Data- och informationsvetenskap -- Datorteknik (hsv//swe)
- NATURAL SCIENCES -- Computer and Information Sciences -- Computer Engineering (hsv//eng)
Nyckelord
- Program processors
- Three dimensional integrated circuits
- Access latency
- Data-communication
- General purpose graphic processing units
- Main memory
- Number of threads
- Memory architecture
Publikations- och innehållstyp
- ref (ämneskategori)
- kon (ämneskategori)
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