ECDR2 : Error Corrector and Detector Relocation Router for Network-on-Chip

• Network-on-chip (NoC) is commonly used in modern many core systems due to its high bandwidth and flexibility. As the manufacturing process keeps scaling, the reliability challenge of NoCs becomes more significant. Error correction code (ECC) is wildly adopted in error correction NoCs to improve the data correctness. At the same time, extra stages are introduced in the router pipeline to embed the error correction capability. As a result, traditional error correction routers suffer from high network latency. Our research was motivated by this limitation and removes the extra pipeline stages introduced for error correction. In this brief, we propose an error correction router, called error corrector and detector relocation router (ECDR2), that achieves both low latency and high error correction capability. The ECDR2 architecture optimizes the pipeline flow of the router, and further improves the network latency. Experimental results show that, compared with the baseline design, ECDR^2 achieves 22.6% and 39.4% less average latency under uniform traffic pattern and Dedup benchmark, respectively in a 8×8 mesh NoC. The circuit area of ECR is also 7.9% less than that of the baseline design under 45nm technology 

Ämnesord

NATURVETENSKAP  -- Data- och informationsvetenskap -- Datorteknik (hsv//swe)

NATURAL SCIENCES  -- Computer and Information Sciences -- Computer Engineering (hsv//eng)

Nyckelord

Error Correction

Latency

Network-on-Chip

Reliability

Pipelines

Routers

Servers

45nm technology

Detector relocation

Error correction capability

Error correction codes

Manufacturing process

Network latencies

Network-on-chip(NoC)

Pipeline stages

Integrated circuit design

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