Fabrication of wire-MOSFETs on silicon-on-insulator substrate

• This paper describes the simulation and fabrication of N-type wire-MOSFETs with a multigate structure fabricated on silicon-on-insulator (SOI) material. Both simulations as well as experiments show that short channel effects (SCE) can be reduced by decreasing the channel width of the transistors below 100 nm. The triple-sided gate generates principally higher potential barriers in the channel, suppressing punch through effects significantly. (C) 2002 Elsevier Science B.V. All rights reserved.

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Nanoteknik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Nano-technology (hsv//eng)

Nyckelord

wire MOSFET

silicon-on-insulator (SOI)

double gate

fully depleted

triple-sided gate structure

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