High level synthesis in DSP ASIC optimization

• In this paper Digital Signal Processing (DSP) system optimization with High Level Synthesis (HLS) environment is presented. To optimize a behavioural VHDL description, commercial SYNT and Synopsys synthesis tools are utilized. The optimization results are improved with a simple rule based preallocator. The coefficient optimization is done in Matlab to provide an efficient implementation of power-of-two and multiply-accumulate based FIR filters. The optimization results are presented using practical filter examples

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Nyckelord

DSP ASIC optimization; Matlab; SYNT synthesis tools; Synopsys synthesis tools; behavioural VHDL description; coefficient optimization; digital signal processing; high level synthesis; multiply-accumulate based FIR filters; power-of-two FIR filters; rule based preallocator; FIR filters; application specific integrated circuits; circuit optimisation; digital filters; digital signal processing chips; high level synthesis

Publikations- och innehållstyp

ref (ämneskategori)

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