Globally asynchronous locally synchronous architecture for large high-performance ASICs

• Clock nets are the major source of power consumption in large, high-performance ASICs and a design bottleneck when it comes to tolerable clock skew. A way to obviate the global clock net is to partition the design into large synchronous blocks each having its own clock. Data with other blocks is exchanged asynchronously using handshake signals. Adopting such a strategy requires a methodology that supports: 1) a partitioning method dividing a design into the number of synchronous blocks such that the gain due to global clock net removal exceeds the communication overhead and 2) synthesis of handshake protocols to implement the data transfer between synchronous blocks. We describe this methodology and present results of applying it to a realistic design done in 0.25 micron, ranging in operating frequencies from 20 MHz to 1 GHz. The results show that the net power savings compared to fully synchronous designs are on an average about 30%

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Nyckelord

0.25 micron;20 MHz to 1 GHz;clock nets;communication overhead;design bottleneck;globally asynchronous locally synchronous architecture;handshake protocols;handshake signals;high-performance ASICs;net power savings;operating frequencies;partitioning method;power consumption;tolerable clock skew;VLSI;application specific integrated circuits;asynchronous circuits;circuit CAD;clocks;integrated circuit design;logic CAD;logic partitioning;protocols

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