On-Chip Stimulus Generator for Gain, Linearity, and Blocking Profile Test of Wideband RF Front Ends

• This paper presents the design and measurement of a stimulus generator suitable for on-chip RF test aimed at gain, 1-dB compression point (CP), and the blocking profile measurement. Implemented in a 90-nm complementary metal-oxide-semiconductor (CMOS), the generator consists of two low-noise voltage-controlled ring oscillators (VCOs) and an adder. It can generate a single-or two-tone signal in a range of 0.9-5.6 GHz with a tone spacing of 3 MHz to 4.5 GHz and adjustable output power. The VCOs are based on symmetrically loaded double-differential delay line architecture. The measured phase noise is -80 dBc/Hz at an offset frequency of 1 MHz for the oscillation frequency of 2.4 GHz. A single VCO consumes 26 mW at 1 GHz while providing -10-dBm power into a 50-Omega load. The silicon area of the complete test circuit including coupling capacitors is only 0.03 mm(2), while a single VCO occupies 0.012 mm(2). The measured gain, 1-dB CP, and blocking profile of the wideband receiver using the on-chip stimulus generator are within +/- 8%, +/- 10%, and +/- 18% of their actual values, respectively. These error values are acceptable for making a pass or fail decision during production testing.

Nyckelord

On-chip RF testing

RF design for testability (DfT)

RF test

stimulus generator

voltage-controlled oscillator (VCO)

TECHNOLOGY

TEKNIKVETENSKAP

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