Evaluation of a surface-channel CCD manufactured in a pinned active-pixel-sensor CMOS process

• This paper presents measurements on a surfacechannel CCD with gates implemented using single-layer polysilicongates. The device was manufactured in a 0.18 μm PINNEDphoto diode CMOS process commercially available from UMC.The CCD was built with a field-plate covering all gates as wellas the space between them, which allows the potential in the gapbetween non-overlapping gates to be manipulated.We present charge transfer efficiency measurements performedat clock frequencies of 1 MHz and 5 MHz, at multiplebackground packet sizes, and field-plate voltages. We furtherpropose and apply a method for separating CTI in four-phaseCCDs due to trapping from the inefficiency stemming from otherphenomena.The measurements show a single stage CTI ranging from 1.7×10−4 with a moderate background charge and substantial fieldplatevoltage, to 0.007 at zero field-plate voltage and the highestbackground charge tested. The CTI can be reduced significantly(more than a factor of 10 in some cases) by applying a significantnegative voltage at the field-plate. This, and the fact that only aminor part of the CTI can be attributed to trapping, indicatesthat the performance of the device is limited by the presence ofpotential hollows in the gaps between the gates.

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TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik -- Annan elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering -- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

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Industrial Electronics

Industriell elektronik

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