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Chemical Mechanical Polishing of Silicon and Silicon Dioxide in Front End Processing

Forsberg, Markus, 1970- (författare)
Uppsala universitet,Fasta tillståndets elektronik
Olsson, Jörgen (preses)
Molarius, Jyrki, Doc (opponent)
VTT Microelectronics Centre
 (creator_code:org_t)
ISBN 9155459951
Uppsala : Acta Universitatis Upsaliensis, 2004
Engelska 65 s.
Serie: Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, 1104-232X ; 991
  • Doktorsavhandling (övrigt vetenskapligt/konstnärligt)
Abstract Ämnesord
Stäng  
  • Chemical mechanical polishing (CMP) has been used for a long time in the manufacturing of prime silicon wafers for the IC industry. Lately, other substrates, such as silicon-on-insulator has become in use which requires a greater control of the silicon CMP process. CMP is used to planarize oxide interlevel dielectric and to remove excessive tungsten after plug filling in the Al interconnection technology. In Cu interconnection technology, the plugs and wiring are filled in one step and excessive Cu is removed by CMP. In front end processing, CMP is used to realize shallow trench isolation (STI), to planarize trench capacitors in dynamic random access memories (DRAM) and in novel gate concepts. This thesis is focused on CMP for front end processing, which is the processing on the device level and the starting material. The effects of dopants, crystal orientation and process parameters on silicon removal rate are investigated. CMP and silicon wafer bonding is investigated. Also, plasma assisted wafer bonding to form InP MOS structures is investigated. A complexity of using STI in bipolar and BiCMOS processes is the integration of STI with deep trench isolation (DTI). A process module to realize STI/DTI, which introduces a poly CMP step to planarize the deep trench filling, is presented. Another investigated front end application is to remove the overgrowth in selectively epitaxially grown collector for a SiGe heterojunction bipolar transistor. CMP is also investigated for rounding, which could be beneficial for stress reduction or to create microoptical devices, using a pad softer than pads used for planarization. An issue in CMP for planarization is glazing of the pad, which results in a decrease in removal rate. To retain a stable removal rate, the pad needs to be conditioned. This thesis introduces a geometrically defined abrasive surface for pad conditioning.

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik -- Annan elektroteknik och elektronik (hsv//swe)
ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering -- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Nyckelord

Electronics
chemical mechanical polishing
chemical mechanical planarization
silicon
silicon dioxide
front end
shallow trench isolation
deep trench isolation
bipolar transistor
BiCMOS
wafer bonding
Elektronik
Electronics
Elektronik

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