A Computational Load-Pull Method for TCAD Optimization of RF-Power Transistors in Bias-Modulation Applications

• In this paper a method for TCAD evaluation of RF-Power transistors for high-efficiency operation using drain bias-modulation is presented. The method is based on large signal time-domain transient computational load-pull. With the method, intrinsic device parasitics and mechanisms affecting device efficiency under drain bias modulation can be investigated and optimized for the application making it very useful for RFIC design. A case study has been done on a CMOS compatible LDMOS. For verification under dynamic operation two-tone signals with varying envelope has been simulated. The results show a possible 15% increase in the efficiency of a modulated signal for the studied device at the expense of increased phase distortion observable also in the time-domain waveforms generated. Since the method is based on TCAD it is also useful in the investigation of e.g. dynamic breakdown during high envelope under bias-modulation operation.

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik -- Annan elektroteknik och elektronik (hsv//swe)

ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering -- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

Nyckelord

MOS integrated circuits

power transistors

radiofrequency integrated circuits

technology CAD (electronics)

CMOS compatible LDMOS

RF-power transistors

RFIC design

TCAD optimization

bias-modulation applications

computational load-pull method

TECHNOLOGY

TEKNIKVETENSKAP

Electronics

Publikations- och innehållstyp

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