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Sökning: id:"swepub:oai:lup.lub.lu.se:318b3739-b54d-4827-b7e3-9b7c537766aa" > Fabrication of Tunn...

Fabrication of Tunnel FETs demonstrating sub-thermal subthreshold slope

Krishnaraja, Abinaya (författare)
Lund University,Lunds universitet,Nanoelektronik,Forskargrupper vid Lunds universitet,Nano Electronics,Lund University Research Groups
Svensson, Johannes (författare)
Lund University,Lunds universitet,Nanoelektronik,Forskargrupper vid Lunds universitet,Nano Electronics,Lund University Research Groups
Lind, Erik (författare)
Lund University,Lunds universitet,NanoLund: Centre for Nanoscience,Annan verksamhet, LTH,Lunds Tekniska Högskola,Nanoelektronik,Forskargrupper vid Lunds universitet,Other operations, LTH,Faculty of Engineering, LTH,Nano Electronics,Lund University Research Groups
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Wernersson, Lars-Erik (författare)
Lund University,Lunds universitet,Nanoelektronik,Forskargrupper vid Lunds universitet,Nano Electronics,Lund University Research Groups
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 (creator_code:org_t)
2019
2019
Engelska.
  • Konferensbidrag (refereegranskat)
Abstract Ämnesord
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  • Tunnel Field Effect Transistor (TFET), based on band-to-band tunneling, overcomes the thermal limit (subthreshold slope (S) > 60 mV/decade) of the MOSFETs by filtering the high-energy Fermi tail, thereby allowing a substantial reduction of supply voltage and power consumption. Despite the steep slope behavior, TFETs can suffer from ambipolarity wherein carriers tunnel into the channel at both high positive and negative gate voltages. In this work, we demonstrate the fabrication of InAs/InGaAsSb/GaSb vertical nanowire TFET devices and present experimental data showcasing suppressed ambipolarity and a minimum S = 39 mV/decade at Vds=0.05V. The nanowires were grown using MOVPE where the 100nm long InAs drain was n-doped with TESn followed by a 100nm undoped InAs channel and a 100nm/300nm DEZn doped InGaAsSb/GaSb source. After growth, the InAs was selectively digitally etched using citric acid to reduce the channel diameter from 40nm to 25nm. The electrostatics was improved, compared to our previously reported devices, with a gate stack of ALD bilayer of 1nm/3nm Al2O3/HfO2 (EOT~1nm) followed by 30nm sputtered W. To decrease the ambipolar conduction, a gate-drain underlap of approximately 20nm was used which widens the tunnel barrier at the drain junction. Since the gate length is defined by the bottom spacer thickness in vertical transistors, the underlap provides a shorter gate positioned close to the source-channel junction. Thus the new process scheme has improved the slope and reduced the OFF current by one order of magnitude compared to our previous devices [1]. [1] E. Memisevic et al., IEEE Trans.ElectronDevices,vol.64,4746–4751, 2017.

Ämnesord

TEKNIK OCH TEKNOLOGIER  -- Elektroteknik och elektronik -- Annan elektroteknik och elektronik (hsv//swe)
ENGINEERING AND TECHNOLOGY  -- Electrical Engineering, Electronic Engineering, Information Engineering -- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)

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