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Vertical InAs Nanow...
Vertical InAs Nanowire Wrap Gate Transistors on Si Substrates
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- Rehnstedt, Carl (författare)
- Lund University,Lunds universitet,Fasta tillståndets fysik,Fysiska institutionen,Institutioner vid LTH,Lunds Tekniska Högskola,Solid State Physics,Department of Physics,Departments at LTH,Faculty of Engineering, LTH
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- Mårtensson, Thomas (författare)
- Lund University,Lunds universitet,Fasta tillståndets fysik,Fysiska institutionen,Institutioner vid LTH,Lunds Tekniska Högskola,Solid State Physics,Department of Physics,Departments at LTH,Faculty of Engineering, LTH
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- Thelander, Claes (författare)
- Lund University,Lunds universitet,Fasta tillståndets fysik,Fysiska institutionen,Institutioner vid LTH,Lunds Tekniska Högskola,Solid State Physics,Department of Physics,Departments at LTH,Faculty of Engineering, LTH
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- Samuelson, Lars (författare)
- Lund University,Lunds universitet,Fasta tillståndets fysik,Fysiska institutionen,Institutioner vid LTH,Lunds Tekniska Högskola,Solid State Physics,Department of Physics,Departments at LTH,Faculty of Engineering, LTH
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- Wernersson, Lars-Erik (författare)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Fasta tillståndets fysik,Fysiska institutionen,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH,Solid State Physics,Department of Physics,Faculty of Engineering, LTH
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(creator_code:org_t)
- 2008
- 2008
- Engelska.
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383. ; 55:11, s. 3037-3041
- Relaterad länk:
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http://dx.doi.org/10...
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https://lup.lub.lu.s...
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https://doi.org/10.1...
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Abstract
Ämnesord
Stäng
- We report on InAs enhancement-mode field-effect transistors integrated directly on Si substrates. The transistors consist of vertical InAs nanowires, grown on Si substrates without the use of metal seed particles, and they are processed with a 50-nm-long metal wrap gate and high-kappa gate dielectric. Device characteristics showing enhancement-mode operation are reported. The output characteristics are asymmetric due to the band alignment and band bending at the InAs/Si interface. The implemented transistor geometry can therefore also serve as a test structure for investigating the InAs/Si heterointerface. From temperature-dependent measurements, we deduce an activation energy of about 200 meV for the TnAs/Si conduction band offset.
Ämnesord
- NATURVETENSKAP -- Fysik -- Den kondenserade materiens fysik (hsv//swe)
- NATURAL SCIENCES -- Physical Sciences -- Condensed Matter Physics (hsv//eng)
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Nyckelord
- nanowires (NWs)
- Field-effect transistor (FET)
- InAs
- on Si
- III-V
- wrap gate
Publikations- och innehållstyp
- art (ämneskategori)
- ref (ämneskategori)
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