Sökning: id:"swepub:oai:research.chalmers.se:f8781173-d953-4590-a68e-8c39d1e760cb" >
Table-Based Total P...
Table-Based Total Power Consumption Estimation of Memory Arrays for Architects
-
- Do, Minh Quang, 1969 (författare)
- Chalmers tekniska högskola,Chalmers University of Technology
-
- Larsson-Edefors, Per, 1967 (författare)
- Chalmers tekniska högskola,Chalmers University of Technology
-
- Bengtsson, Lars, 1958 (författare)
- Chalmers tekniska högskola,Chalmers University of Technology
-
(creator_code:org_t)
- Berlin, Heidelberg : Springer Berlin Heidelberg, 2004
- 2004
- Engelska.
-
Ingår i: Lecture Notes in Computer Science (LNCS) , Springer Verlag. - Berlin, Heidelberg : Springer Berlin Heidelberg. ; 3254:1, s. 869-878
- Relaterad länk:
-
http://dx.doi.org/10...
-
visa fler...
-
https://doi.org/10.1...
-
https://research.cha...
-
visa färre...
Abstract
Ämnesord
Stäng
- In this paper, we propose the White-box Table-based Total Power Consumption (WTTPC) estimation approach that offers both rapid and accurate architecture-level power estimation models for some processor components with regular structures, such as SRAM arrays, based on WTTPC-tables ofpower values. A comparison of power estimates obtained from the proposed approach against circuit-level HSPICE power values for a 64-b conventional 6T-SRAM memory array implemented in a commercial 0.13-um CMOS technology process shows a 98% accuracy of the WTTPC approach.
Ämnesord
- NATURVETENSKAP -- Data- och informationsvetenskap (hsv//swe)
- NATURAL SCIENCES -- Computer and Information Sciences (hsv//eng)
Publikations- och innehållstyp
- kon (ämneskategori)
- ref (ämneskategori)