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- Larsson, Anders, 1977-
(författare)
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System-on-Chip Test Scheduling and Test Infrastructure Design
- 2005
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Licentiatavhandling (övrigt vetenskapligt)abstract
- There are several challenges that have to be considered in order to reduce the cost of System-on-Chip (SoC) testing, such as test application time, chip area overhead due to hardware introduced to enhance the testing, and the price of the test equipment. In this thesis the test application time and the test infrastructure hardware overhead of multiple-core SoCs are considered and two different problems are addressed. First, a technique that makes use of the existing bus structure on the chip for transporting test data is proposed. Additional buffers are inserted at each core to allow test application to the cores and test data transportation over the bus to be performed asynchronously. The non-synchronization of test data transportation and test application makes it possible to perform concurrent testing of cores while test data is transported in a sequence. A test controller is introduced, which is responsible for the invocation of test transportations on the bus. The hardware cost, introduced by the buffers and test controller, is minimized under a designer-specified test time constraint. This problem has been solved optimally by using a Constraint Logic Programming formulation, and a tabu search based heuristic has also been implemented to generate quickly near-optimal solutions. Second, a technique to broadcast tests to several cores is proposed, and the possibility to use overlapping test vectors from different tests in a SoC is explored. The overlapping tests serve as alternatives to the original, dedicated, tests for the individual cores and, if selected, they are broadcasted to the cores so that several cores are tested concurrently. This technique allows the existing bus structure to be reused; however, dedicated test buses can also be introduced in order to reduce the test time. Our objective is to minimize the test application time while a designer-specified hardware constraint is satisfied. Again Constraint Logic Programming has been used to solve the problem optimally. Experiments using benchmark designs have been carried out to demonstrate the usefulness and efficiency of the proposed techniques.
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| 3. |
- Larsson, Anders
(författare)
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High frequency distortion in power grids due to electronic equipment
- 2006
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Licentiatavhandling (övrigt vetenskapligt)abstract
- Power quality is a subject that has received a lot of attention during the last 10 to 20 years, both in industry and in academia. Power quality concerns interaction between the power grid and its customers and between the power grid and equipment connected to it, reflected in voltages and currents. Research and other developments in this area have to a great extent concentrated on relatively slow and low-frequency phenomena, with the main emphasis being on voltage dips (reductions in voltage magnitude with duration between about 50 ms and several seconds) and low-frequency harmonics (waveform distortion by frequency components up to about 2 kHz). These phenomena are reasonably well understood. For higher-frequency phenomena there is no such general understanding. There are a number of reasons for looking closer into this frequency range, including increased distortion by energy-efficient equipment, interference with equipment such as that used for communications, reduced service life of equipment, the availability of measurement and analysis tools, and pure scientific curiosity. This licentiate thesis addresses voltage and current distortion in low- voltage networks in the frequency range between 2 kHz and 1 MHz. The report starts with a general overview of power quality and power-quality disturbances. This part is mainly a review of existing knowledge. The report continues with a philosophical discussion of measurement and analysis of power-quality disturbances. The objectiveness of the analysis methods is especially addressed. The importance of understanding the limitations posed by measurement standards and commonly used analysis methods is emphasized. The choice of measurement and analysis tool has the potential to influence the conclusions drawn from a study. Different analysis and presentation tools are discussed for disturbances in the frequency band of interest. Where possible, a range of methods should be used. Next to the commonly used time- and frequency-domain presentations, the spectrogram or time-frequency-domain is introduced as a useful tool. The measurement technology used for obtaining sampled voltage and current waveforms is discussed. Measurements have been performed on the current drawn by individual devices and by groups of devices. These measurements have been performed mainly in a controlled laboratory environment. Voltage measurements have mainly been performed at a number of locations in the field. Both current and voltage measurements are described in detail in this report, together with the measurement results. The main contribution of this licentiate report is in the systematic analysis of disturbances in the frequency range between 2 kHz and 1 MHz. The spectrogram has proven a suitable tool for analyzing and visualizing these disturbances. Further knowledge is obtained on the disturbances arising from fluorescent lamps with high-frequency ballasts. Contrary to conventional knowledge, the main concern is in the so-called zero-crossing distortion. The level of this distortion component demonstrates a linear increase with the number of devices.
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