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Träfflista för sökning "swepub ;pers:(Larsson Anders);pers:(Larsson Erik 1966)"

Sökning: swepub > Larsson Anders > Larsson Erik 1966

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1.
  • Larsson, Anders, 1977-, et al. (författare)
  • A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
  • 2007
  • Ingår i: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems,2007. - Krakow, Poland : IEEE Computer Society Press. - 1-4244-1162-9 - 1-4244-1162-9 ; s. 61
  • Konferensbidrag (refereegranskat)abstract
    • The increasing cost for System-on-Chip (SOC) testing is mainly due to the huge test data volumes that lead to long test application time and require large automatic test equipment (ATE) memory. Test compression and test sharing have been proposed to reduce the test data volume, while test infrastructure and concurrent test scheduling have been developed to reduce the test application time. In this work we propose an integrated test scheduling and test infrastructure design approach that utilizes both test compression and test sharing as basic mechanisms to reduce test data volumes. In particular, we have developed a heuristic to minimize the test application time, considering different alternatives of test compression and sharing, without violating a given ATE memory constraint. The results from the proposed Tabu Search based heuristic have been validated using benchmark designs and are compared with optimal solutions.
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2.
  • Larsson, Anders, 1977-, et al. (författare)
  • A Technique for Optimization of System-on-Chip Test Data Transportation
  • 2004
  • Ingår i: 9th IEEE European Test Symposium,2004. ; s. 179-180
  • Konferensbidrag (refereegranskat)abstract
    • We propose a Tabu-search-based technique for time-constrained SOC (System-on-Chip) test data transportation. The technique makes use of the existing bus structure, where the advantage is, compared to adding dedicated test buses, that no additional routing is needed. In order to speed up the testing and to fulfill the time constraint, we introduce a buffer at each core, which in combination with dividing tests into smaller packages allows concurrent application of tests on a sequential bus. Our technique minimizes the combined cost of the added buffers and the test control logic. We have implemented the technique, and experimental results indicate that it produces high quality results at low computational cost.
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3.
  • Larsson, Anders, 1977-, et al. (författare)
  • Buffer and Controller Minimization for Time-Constrained Testing of System-On-Chip
  • 2003
  • Ingår i: 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03,2003. - Cambridge, MA, USA : IEEE Computer Society Press. ; s. 385
  • Konferensbidrag (refereegranskat)abstract
    • Test scheduling and Test Access Mechanism (TAM)design are two important tasks in the development of a System-on-Chip (SOC)test solution.Previous test scheduling techniques assume a dedicated designed TAM which have the advantage of high exibility in the scheduling process. However,hardware verhead for implementing the TAM and additional routing is required of the TAMs.In this paper we propose a technique that makes use of the existing functional buses for the test data transportation inside the SOC.We have dealt with the test scheduling problem with this new assumption and developed a technique to minimize the test-controller and buffer size for a bus- based multi-core SOC.We have solved the problem by using a constraint logic pr gramming (CLP) technique and demonstrated the ef ciency of our approach by running experiments on benchmark designs.
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4.
  • Larsson, Anders, 1977-, et al. (författare)
  • Core-Level Expansion of Compressed Test Patterns
  • 2008
  • Ingår i: 17th Asian Test Symposium ATS,2008. - Sapporo, JAPAN : IEEE Computer Society. ; s. 277
  • Konferensbidrag (refereegranskat)abstract
    •  The increasing test-data volumes needed for the testing of system-on-chip (SOC) integrated circuits lead to long test-application times and high tester memory requirements. Efficient test planning and test-data compression are therefore needed. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. This implies that for a given set of compression schemes, there is no compression scheme that is the optimal with respect to test time reduction and test-data compression at all TAM widths. We therefore propose a technique where we integrate core wrapper design, test architecture design and test scheduling with test-data compression technique selection for each core in order to minimize the SOC test-application time and the test-data volume. Experimental results for several SOCs crafted from industrial cores demonstrate that the proposed method leads to significant reduction in test-data volume and test time.
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5.
  • Larsson, Anders, 1977-, et al. (författare)
  • Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
  • 2005
  • Ingår i: 8th Euromicro Conference on Digital System Design DSD2005,2005. - Porto, Portugal : IEEE Computer Society Press. - 0-7695-2433-8 ; s. 403
  • Konferensbidrag (refereegranskat)abstract
    • The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the chip. Having a powerful TAM will shorten the test time, but it costs large silicon area to implement it. Hence, it is important to have an efficient TAM with minimal required hardware overhead. We propose a technique that makes use of the existing bus structure with additional buffers inserted at each core to allow test application to the cores and test data transportation over the bus to be performed asynchronously. The non-synchronization of test data transportation and test application makes it possible to perform concurrent testing of cores while test data is transported in a sequence. We have implemented a Tabu search based technique to optimize our test architecture, and the experimental results indicate that it produces high quality results at low computational cost.
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6.
  • Larsson, Anders, 1977-, et al. (författare)
  • Optimized Integration of Test Compression and Sharing for SOC Testing
  • 2007
  • Ingår i: Design, Automation, and Test in Europe Conference DATE07,2007. - Nice, France : IEEE Computer Society Press. - 978-3-9810801-2-4 ; s. 207
  • Konferensbidrag (refereegranskat)abstract
    • The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requirements. TAT and ATE memory requirement can be reduced by test architecture design, test scheduling, sharing the same tests among several cores, and test data compression. We propose, in contrast to previous work that addresses one or few of the problems, an integrated framework with heuristics for sharing and compression and a Constraint Logic Programming technique for architecture design and test scheduling that minimizes the TAT without violating a given ATE memory constraint. The significance of our approach is demonstrated by experiments with ITC-02 benchmark designs.
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7.
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8.
  • Larsson, Anders, 1977-, et al. (författare)
  • SOC Test Scheduling with Test Set Sharing and Broadcasting
  • 2005
  • Ingår i: IEEE Asian Test Symposium,2005. - Kolkata, India : IEEE Computer Society Press. - 0-7695-2481-8 ; s. 162
  • Konferensbidrag (refereegranskat)abstract
    • Due to the increasing test data volume needed to test core-based System-on-Chip, several test scheduling techniques minimizing the test application time have been proposed. In contrast to approaches where a fixed test set for each core is assumed, we explore the possibility to use overlapping test patterns from the tests in the system. The overlapping tests serves as alternatives to the original dedicated test for the cores and, if selected, they are transported to the cores in a broadcasted manner so that several cores are tested concurrently. We have made use of a Constraint Logic Programming technique to select suitable tests for each core in the system and schedule the selected tests such that the test application time is minimized while designer-specified hardware constraints are satisfied. The experimental results indicate that we can on average reduce the test application time with 23%.
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9.
  • Larsson, Anders, 1977-, et al. (författare)
  • Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
  • 2008
  • Ingår i: Design, Automation, and Test in Europe DATE 2008,2008. - Munich, Germany : IEEE Computer Society Press. - 978-3-9810801-3-1 - 978-3-9810801-4-8 ; s. 188
  • Konferensbidrag (refereegranskat)abstract
    • The ever-increasing test data volume for core-based system-on-chip (SOC) integrated circuits is resulting in high test times and excessive tester memory requirements. To reduce both test time and test data volume, we propose a technique for test-architecture optimization and test scheduling that is based on core-level expansion of compressed test patterns. For each wrapped embedded core and its decompressor, we show that the test time does not decrease monotonically with the width of test access mechanism (TAM) at the decompressor input. We optimize the wrapper and decompressor designs for each core, as well as the TAM architecture and the test schedule at the SOC level. Experimental results for SOCs crafted from several industrial cores demonstrate that the proposed method leads to significant reduction in test data volume and test time, especially when compared to a method that does not rely on core-level decompression of patterns.
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10.
  • Larsson, Erik, 1966-, et al. (författare)
  • Student-oriented Examination in a Computer Architecture Course
  • 2004
  • Ingår i: 9th Annual Conference on Innovation and Technology in Computer Science Education,2004. ; s. 245-245
  • Konferensbidrag (refereegranskat)abstract
    • Learning is a highly individual process. Some prefer learning by reading the course material, others learn best by listening to a lecture, whilesome like to learn in a trial-and-error way by themselves in a laboratory assignment. A good learning scheme is individual. A scheme that is good for some persons might not at all be good scheme for someone else. It is important to understand your own personal way to learn, but also when organizing a course individual learning alternatives should be acknowledged.Examination in a course can be seen as a test occasion or as a learning occasion. Traditionally, examination has been an occasion where knowledge is tested. Written exams can be used to test the theory and laboratory work to test practical aspects of the course material. For laboratory work the distinction between learning and test of learning is somewhat unclear. The learning and the test of learning are mixed. However, in general, examination can be seen as an occasion to learn and/or to test knowledge. We have, in a Computer Architecture course, taken the view that (1) learning is an individual process, and (2) that examination is a learning occasion. The consequence of our view (1)+(2) is basically that examination should be individual, or student-oriented. Alternatives to traditional examination is also supported when taking gender, cultural, and age perspectives. We therefore developed two examination tracks where the students in the beginning of the course decided what track to follow. Common for both tracks is that credits are given that can be counted for in the written exam
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