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1.
  • Bjureus, P., et al. (författare)
  • Modeling of mixed control and dataflow systems in MASCOT
  • 2001
  • Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - 1063-8210. ; 9:5, s. 690-703
  • Tidskriftsartikel (refereegranskat)abstract
    • The Matlab and SDL Codesign Technique (MASCOT) method integrates modeling of data flow and control dominated parts at the system level. Based on the established languages specification and description language (SDL) and Matlab, MASCOT provides a modeling and simulation technique which realizes the communication and synchronization between the two domains. Moreover, it offers modeling guidelines for a disciplined and efficient way of using the technique. Most of the tedious details of modeling synchronization and communication is handled automatically and is transparent to the user. Consequently, the user can focus on the application and on the important tradeoffs to be made at the system level.
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3.
  • Hellberg, Lars, et al. (författare)
  • System oriented VLSI curriculum at KTH
  • 1997
  • Ingår i:  . ; s. 57-59
  • Konferensbidrag (refereegranskat)abstract
    • This paper describes the restructuring of VLSI education at the Royal Institute of Technology (KTH). Changing needs of industry, advances in technology and design methodology has required a significant reorganization of VLSI education with combined emphasis on system issues and associated physical constraints. We present here a course structure which will address, in parallel fashion, the key design issues for future system products
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4.
  • Hemani, Ahmed, et al. (författare)
  • High-level synthesis of control and memory intensive communication systems
  • 1995
  • Ingår i:  . ; s. 185-191
  • Konferensbidrag (refereegranskat)abstract
    • Communication sub-systems that deal with switching, routing and protocol implementation often have their functionality dominated by control logic and interaction with memory. Synthesis of such Control and Memory Intensive Systems (hereafter abbreviated to CMISTs) poses demands that in the past have not been met satisfactorily by general purpose high-level synthesis (HLS) tools and have led to several research efforts to address these demands. In this paper we: characterise CMISTs from the synthesis viewpoint; present a synthesis methodology adapted for CMISTs; present the Operation and Maintenance (OAM) Protocol of the ATM, its modelling in VHDL and synthesis aspects of the VHDL model; present the results of applying the synthesis methodology to the OAM as a test case-the results are compared to that obtained using the not adapted general purpose High-level synthesis tool; prove the efficacy of the proposed synthesis methodology by applying it to an industrial design and comparing our results to the results from two commercial HLS tools and to the results obtained by designing manually at register-transfer level
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6.
  • Kumar, Shashi, et al. (författare)
  • A network on chip architecture and design methodology
  • 2002
  • Ingår i: VLSI 2002 : IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI - NEW PARADIGMS FOR VLSI SYSTEMS DESIGN. - IEEE conference proceedings. - 0-7695-1486-3 ; s. 105-112
  • Konferensbidrag (refereegranskat)abstract
    • We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology. The NOC architecture is a m x n mesh of switches and resources are placed on the slots formed by the switches. We assume a direct layout of the 2-D mesh of switches and resources providing physical- architectural level design integration. Each switch is connected to one resource and four neighboring switches, and each resource is connected to one switch. A resource can be a processor core, memory, an FPGA, a custom hardware block or any other intellectual property (LP) block, which fits into the available slot and complies with the interface of the NOC. The NOC architecture essentially is the onchip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack. We define the concept of a region, which occupies an area of any number of resources and switches. This concept allows the NOC to accommodate large resources such as large memory banks, FPGA areas, or special purpose computation resources such as high performance multiprocessors. The NOC design methodology consists of two phases. In the first phase a concrete architecture is derived from the general NOC template. The concrete architecture defines the number of switches and shape of the network, the kind and shape of regions and the number and kind of resources. The second phase maps the application onto the concrete architecture to form a concrete product.
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7.
  • O'Nils, Mattias, et al. (författare)
  • Device driver and DMA controller synthesis from HW /SW communication protocol specifications
  • 2001
  • Ingår i: Design automation for embedded systems. - Kluwer Academic Publishers. - 0929-5585. ; 6:2, s. 177-205
  • Tidskriftsartikel (refereegranskat)abstract
    • We have separated the information required for HW /SW interface synthesis into three parts, the protocol specification, the operating system related information, and the processor related information. From these inputs a synthesis tool generates (a) device driver functions or (b) a combination of device driver functions and a DMA controller, depending on a designer's decision. The clean separation of information facilitates (1) efficient design space exploration with combinations of different processors, operating systems and protocols, and (2) maintaining a large number of different versions and variants of HW /SW interfaces by synthesising them on demand. Protocols are specified as a grammar, which is fully independent of architecture and implementation. From this the synthesis tool generates device driver code in C and /or synthesizable RTL code in VHDL for DMA controllers. After the initial selection of implementation alternatives the presented methods are fully automated. Its computational complexity is quadratic in terms of the number of states. With real-life examples we show that the quality of the generated code is close to hand written quality in terms of performance, area and code size.
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8.
  • O’Nils, Mattias, et al. (författare)
  • Operating System Sensitive Device Driver Synthesis from Implementation Independent Protocol Specification
  • 1999
  • Ingår i: Proceedings of Design Automation and Test in Europe (DATE). ; s. 562-568
  • Konferensbidrag (refereegranskat)abstract
    • We present a method for generation of the software part of a HW/SW interface (i.e. the device drivers), which separatesthe behaviour of the interface from the architecture dependent parts. We do this by modelling the behaviour in ProGram (a grammar based protocol specification language) and capture the processor and OS kernel parts in separate libraries. By separating the behaviour from thearchitectural specific parts, compared to other approaches up to 50% development time can be saved the first time thecomponent is used, and up to 98% for each time the interfaced component is reused.
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