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  • Resultat 1-10 av 323
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1.
  • Bjureus, P., et al. (författare)
  • Modeling of mixed control and dataflow systems in MASCOT
  • 2001
  • Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - 1063-8210. ; 9:5, s. 690-703
  • Tidskriftsartikel (refereegranskat)abstract
    • The Matlab and SDL Codesign Technique (MASCOT) method integrates modeling of data flow and control dominated parts at the system level. Based on the established languages specification and description language (SDL) and Matlab, MASCOT provides a modeling and simulation technique which realizes the communication and synchronization between the two domains. Moreover, it offers modeling guidelines for a disciplined and efficient way of using the technique. Most of the tedious details of modeling synchronization and communication is handled automatically and is transparent to the user. Consequently, the user can focus on the application and on the important tradeoffs to be made at the system level.
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4.
  • Jafari, Fahimeh, et al. (författare)
  • Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip
  • 2016
  • Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - IEEE. - 1063-8210. ; 24:12, s. 3387-3400
  • Tidskriftsartikel (refereegranskat)abstract
    • We propose an approach for computing the end-to-end delay bound of individual variable bit-rate flows in an First Input First Output multiplexer with aggregate scheduling under weighted round robin (WRR) policy. To this end, we use a network calculus to derive per-flow end-to-end equivalent service curves employed for computing least upper delay bounds (LUDBs) of the individual flows. Since the real-time applications are going to meet guaranteed services with lower delay bounds, we optimize the weights in WRR policy to minimize the LUDBs while satisfying the performance constraints. We formulate two constrained delay optimization problems, namely, minimize-delay and multiobjective optimization. Multiobjective optimization has both the total delay bounds and their variance as the minimization objectives. The proposed optimizations are solved using a genetic algorithm. A video object plane decoder case study exhibits a 15.4% reduction of the total worst case delays and a 40.3% reduction on the variance of delays when compared with round robin policy. The optimization algorithm has low run-time complexity, enabling quick exploration of the large design spaces. We conclude that an appropriate weight allocation can be a valuable instrument for the delay optimization in on-chip network designs.
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5.
  • O’Nils, Mattias, et al. (författare)
  • Device driver and DMA controller synthesis from HW /SW communication protocol specifications
  • 2001
  • Ingår i: Design automation for embedded systems. - 0929-5585. ; 6:2, s. 177-205
  • Tidskriftsartikel (refereegranskat)abstract
    • We have separated the information required for HW /SW interface synthesis into three parts, the protocol specification, the operating system related information, and the processor related information. From these inputs a synthesis tool generates (a) device driver functions or (b) a combination of device driver functions and a DMA controller, depending on a designer’s decision. The clean separation of information facilitates (1) efficient design space exploration with combinations of different processors, operating systems and protocols, and (2) maintaining a large number of different versions and variants of HW /SW interfaces by synthesising them on demand. Protocols are specified as a grammar, which is fully independent of architecture and implementation. From this the synthesis tool generates device driver code in C and /or synthesizable RTL code in VHDL for DMA controllers. After the initial selection of implementation alternatives the presented methods are fully automated. Its computational complexity is quadratic in terms of the number of states. With real-life examples we show that the quality of the generated code is close to hand written quality in terms of performance, area and code size.
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6.
  • Raudvere, Tarvo, et al. (författare)
  • The ForSyDe semantics
  • 2002
  • Ingår i: Proceedings of Swedish System-on-Chip Conference.
  • Konferensbidrag (refereegranskat)
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  • Tammemäe, Kalle, et al. (författare)
  • AKKA: : A Tool-kit for Cosynthesis and Prototyping
  • 1996
  • Ingår i: Hardware-Software Cosynthesis for Reconfigurable Systems, IEE Colloquium, Bristol 22 Feb. 1996. ; s. 8/1-8/8
  • Konferensbidrag (övrigt vetenskapligt)abstract
    • Shortened design and life time of embedded systems has motivated active research in HW/SW co-design area, together with evolution of relatively long-life of reconfigurable HW. In this paper we present Akka1[1][2] - a set of tools for design space exploration, co-simulation and co-synthesis with two industrial examples from the telecommunication field - Maintenance functionality of the ATM protocol and Channel decoder functionality of a D-AMPS base station. For fast prototyping we have selected Xilinx XC4013 FPGA based board from Virtual Computer Corporation. The board is connected to the system bus (SBus) of the host computer.
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